MCP3910A1T-ESLASHML datasheet(71/86 Pages) MICROCHIP

71 / 86 page

 2012-2014 Microchip Technology Inc.

DS20005116B-page 71

MCP3910

bit 21-20

DITHER<1:0>:

Control for dithering circuit for idle tones cancellation and improved THD on all channels

= Dithering ON, Strength = Maximum (Default)

= Dithering ON, Strength = Medium

= Dithering ON, Strength = Minimum

= Dithering turned OFF

bit 19-18

BOOST<1:0>:

Bias Current Selection for all ADCs (impacts achievable maximum sampling speed, see

Table 5-2)

= All channels have current x 2

= All channels have current x 1 (Default)

= All channels have current x 0.66

= All channels have current x 0.5

bit 17-16

PRE<1:0>

Analog Master Clock (AMCLK) Prescaler Value

= AMCLK = MCLK/8

= AMCLK = MCLK/4

= AMCLK = MCLK/2

= AMCLK = MCLK (Default)

bit 15-13

OSR<2:0>

Oversampling Ratio for Delta Sigma A/D Conversion (ALL CHANNELS, f

d / fS)

111

= 4096 (f

d = 244 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

110

= 2048 (f

d = 488 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

101

= 1024 (f

d = 976 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

100

= 512 (f

d = 1.953 ksps for MCLK = 4 MHz, fs =AMCLK = 1 MHz)

011

= 256 (f

d = 3.90625 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) (Default)

010

= 128 (f

d = 7.8125 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz)

001

= 64 (f

d = 15.625 ksps for MCLK = 4 MHz, fs =AMCLK = 1 MHz)

000

= 32 (f

d = 31.25 ksps for MCLK = 4 MHz, fs =AMCLK =1 MHz)

bit 12-8

Unimplemented:

Read as ‘0’

bit 7-0

VREFCAL<7:0>:

Internal Voltage Temperature coefficient VREFCAL<7:0> value. (See Section 5.6.3

“Temperature compensation (VREFCAL<7:0>)”

for complete description).

CONFIG0 REGISTER (CONTINUED)

MCP3910A1T-E/ML Datenblatt(PDF) 71 Page - Microchip Technology

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