WM8281ECSSLASHR datasheet(278/392 Pages) CIRRUS

278 / 392 page

WM8281

278

Rev 4.0

If the above equations produce an integer value for N.K, then the value of FLLn_FRATIO should be

adjusted to a different, odd-number division (eg. divide by 3), and the value of N.K re-calculated. A

non-integer value of N.K is recommended for best performance of the FLL. (If possible, the

FLLn_FRATIO value should be decreased to the nearest alternative odd-number division. If a suitable

lower value does not exist, FLLn_FRATIO should be increased to the nearest odd-number division

instead.)

After the value of FLLn_FRATIO has been determined, the input frequency, FREF, must be compared

with the maximum frequency limit noted in Table 104. If the input frequency (after division by

FLLn_REFCLK_DIV) is higher than the applicable limit, then the FLLn_REFCLK_DIV division ratio

should be increased, and the value of N.K re-calculated. (Note that the same value of FLLn_FRATIO

as already calculated should be used, when deriving the new value of N.K.)

FLLn_FRATIO

REFERENCE FREQUENCY

FREF - MAXIMUM VALUE

0h (divide by 1)

11.5 MHz

1h (divide by 2)

6.144 MHz

2h (divide by 3)

3h (divide by 4)

3.072 MHz

4h (divide by 5)

5h (divide by 6)

2.8224 MHz

6h (divide by 7)

7h (divide by 8)

1.536 MHz

8h (divide by 9)

9h (divide by 10)

Ah (divide by 11)

Bh (divide by 12)

Ch (divide by 13)

Dh (divide by 14)

Eh (divide by 15)

Fh (divide by 16)

768 kHz

Table 104 Maximum FLL input frequency (function of FLLn_FRATIO)

The value of N is held in the FLLn_N register field.

The value of K is determined by the ratio FLLn_THETA / FLLn_LAMBDA.

The FLLn_N, FLLn_THETA and FLLn_LAMBDA fields are all coded as integers (LSB = 1).

If the FLLn_N or FLLn_THETA registers are updated while the FLL is enabled (FLLn_ENA=1), then

the new values will only be effective when a ‘1’ is written to the FLLn_CTRL_UPD bit. This makes it

possible to update the two registers simultaneously, without disabling the FLL.

Note that, when the FLL is disabled (FLLn_ENA=0), then the FLLn_N and FLLn_THETA registers can

be updated without writing to the FLLn_CTRL_UPD bit.

The values of FLLn_THETA and FLLn_LAMBDA can be calculated as described later.

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