WM8281ECSSLASHR datasheet(276/392 Pages) CIRRUS

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WM8281

276

Rev 4.0

MCLK2

MCLK1

FLLn_REFCLK_SRC

(270MHz

≤ Fvco ≤ 312MHz)

FVCO

FOUT

Divide by

FLLn_OUTDIV

Divide by 2, 3 .. 7

FLLn_ENA

(FLL Enable)

FLLn,

AIFnBCLK,

AIFnRXLRCLK

Divide by 1, 2, 4 or 8

Divide by

FLLn_REFCLK_DIV

FREF < 13.5MHz

FREF

Multiply by

N.K

Multiply by

FLLn_FRATIO

Multiply by

1, 2, 3

… 16

Main FLL path

FLLn_SYNCCLK_SRC

N.K = FLLn_N +

FLLn_THETA

FLLn_LAMBDA

N.K (Sync) = FLLn_SYNC_N +

FLLn_SYNC_THETA

FLLn_SYNC_LAMBDA

FLLn_SYNC_ENA

(FLL Synchroniser Enable)

SLIMCLK

SLIMCLK_REF_GEAR

Automatic

Divider

Divide by

FLLn_SYNCCLK_DIV

Divide by 1, 2, 4 or 8

FSYNC < 13.5MHz

FSYNC

Multiply by

N.K (Sync)

Multiply by

FLLn_SYNC_

FRATIO

Multiply by

1, 2, 4, 8 or 16

FLL Synchroniser path

FGPIO

Divide by 7, 8 .. 127

Divide by

FLLn_GPCLK_DIV

Figure 71 FLL Configuration

The procedure for configuring the FLL is described below. Note that the configuration of the main FLL

path and the FLL Synchroniser path are very similar. One or both paths must be configured,

depending on the application requirements:



If a single clock input reference is used, then only the main FLL path should be used.



If the input reference to the main FLL is intermittent, or may be interrupted unexpectedly,

then only the main FLL path should be used.



If two clock input references are used, then the constant or low-noise clock is configured on

the main FLL path, and the high-accuracy clock is configured on the FLL synchroniser path.

Note that the synchroniser input must be synchronous with the audio data.

The following description is applicable to FLL1 and FLL2. The associated register control fields are

described in Table 106 and Table 107 respectively.

The main input reference is selected using FLLn_REFCLK_SRC. The synchroniser input reference is

selected using FLLn_SYNCCLK_SRC. The available options in each case comprise MCLK1, MCLK2,

SLIMCLK, AIFnBCLK, AIFnRXLRCLK, or the output from another FLL.

The SLIMCLK reference is controlled by an adaptive divider on the external SLIMCLK input. The

divider automatically adapts to the SLIMbus Clock Gear, to provide a constant reference frequency for

the FLL. See “SLIMbus Interface Control” for details.

The FLLn_REFCLK_DIV field controls a programmable divider on the main input reference. The

FLLn_SYNCCLK_DIV field controls a programmable divider on the synchroniser input reference.

Each input can be divided by 1, 2, 4 or 8. These registers should be set to bring each reference down

to 13.5MHz or below. For best performance, it is recommended that the highest possible frequency -

within the 13.5MHz limit - should be selected. (Note that additional guidelines also apply, as described

below.)

The FLL output frequency, relative to the main input reference FREF, is directly determined from

FLLn_FRATIO, FLLn_OUTDIV and the real number represented by N.K.

The integer value, N, is held in the FLLn_N register field. The fractional portion, K, is determined by

the ratio FLLn_THETA / FLLn_LAMBDA.

WM8281ECS/R Datenblatt(PDF) 276 Page - Cirrus Logic

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