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WM8281ECS/R Datenblatt(PDF) 295 Page - Cirrus Logic |
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WM8281ECS/R Datenblatt(HTML) 295 Page - Cirrus Logic |
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295 / 392 page ![]() WM8281 Rev 4.0 295 4-WIRE (SPI) CONTROL MODE The 4-wire (SPI) Control Interface mode is supported on CIF1 only, and uses the corresponding SS ¯¯ , SCLK, MOSI and MISO pins. The MISO output pin can b e configured as CMOS or ‘Wired OR’, as described in Table 113. In CMOS mode, MISO is driven low when not outputting register data bits. In ‘Wired OR’ mode, MISO is undriven (high impedance) when not outputting register data bits. In Write operations (R/W=0), all MOSI bits are driven by the controlling device. In Read operations (R/W=1), the MOSI pin is ignored following receipt of the valid register address. MISO is driven by the WM8281. Continuous read and write modes enable multiple register operations to be scheduled faster than is possible with single register operations. The auto-increment function supports selectable address increments for each successive register access. This function is controlled using the SPI_AUTO_INC register. Auto-increment (by 1) is enabled by default, as described in Table 113. When auto-increment is enabled, the WM8281 will increment the register address at the end of the sequences illustrated below, and every 16 clock cycles thereafter, for as long as SS ¯¯ is held low and SCLK is toggled. Successive data words can be input/output every 16 clock cycles. The 4-wire (SPI) protocol is illustrated in Figure 79 and Figure 80. A30 MOSI SCLK 31-bit control register address 16-bit control register data R/W SS A29 X X X X B14 B0 B1 A1 A0 B15 16-bit padding Figure 79 Control Interface 4-wire (SPI) Register Write A30 MOSI SCLK 31-bit control register address 16-bit control register data MISO R/W SS A29 X X X X X X X B14 B0 B1 A1 A0 X B15 16-bit padding Figure 80 Control Interface 4-wire (SPI) Register Read |
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