WM8281ECSSLASHR datasheet(296/392 Pages) CIRRUS

296 / 392 page

WM8281

296

Rev 4.0

CONTROL WRITE SEQUENCER

The Control Write Sequencer is a programmable unit that forms part of the WM8281 control interface

logic. It provides the ability to perform a sequence of register write operations with the minimum of

demands on the host processor - the sequence may be initiated by a single operation from the host

processor and then left to execute independently.

Default sequences for pop-suppressed start-up and shut-down of each headphone/earpiece output

driver are provided (these are scheduled automatically when the respective output paths are enabled

or disabled). Other control sequences can be programmed, and may be associated with Jack Detect,

MICDET Clamp, DRC, Wake-Up or Sample Rate Detection functions - these sequences are

automatically scheduled whenever a corresponding event is detected.

When a sequence is initiated, the sequencer performs a series of pre-defined register writes. The

‘start index’ of a control sequence within the sequencer’s memory may be commanded directly by the

host processor.

The applicable ‘start index’ for each of the sequences associated with Jack Detect,

MICDET Clamp, DRC, Wake-Up or Sample Rate Detection is held in a user-programmed control

The Control Write Sequencer may be triggered in a number of ways, as described above. Multiple

sequences will be queued if necessary, and each is scheduled in turn. When all of the queued

sequences have completed, the sequencer stops, and an Interrupt status flag is asserted.

A valid clock (SYSCLK) must be enabled whenever a Control Write Sequence is scheduled. See

“Clocking and Sample Rates” for further details.

INITIATING A SEQUENCE

The Register fields associated with running the Control Write Sequencer are described in Table 116.

The Write Sequencer is enabled using the WSEQ_ENA bit. The index location of the first command in

the selected sequence is held in the WSEQ_START_INDEX register.

Writing a ‘1’ to the WSEQ_START bit commands the sequencer to execute a control sequence,

starting at the given index. Note that, if the sequencer is already running, then the WSEQ_START

command will be queued, and will be executed later when the sequencer becomes available.

Note that the mechanism for queuing multiple sequence requests has some limitations, when using

the WSEQ_START bit to trigger the write sequencer. If a sequence is initiated using the

WSEQ_START bit, no other control sequences should be triggered until the sequence completes.

The WSEQ_BUSY bit (described in Table 121) provides an indication of the sequencer status, and

can be used to confirm that sequence has completed. Control sequences triggered by another other

method are queued if necessary, and scheduled in turn.

The Write Sequencer can be interrupted by writing a

‘1’ to the WSEQ_ABORT bit. Note that this

command will only abort a sequence that is currently running; if other sequence commands are

pending and not yet started, these sequences will not be aborted by writing to the WSEQ_ABORT bit.

The Write Sequencer stores up to 510 register write commands. These are defined in Registers

R12288 (3000h) to R13307 (33FBh). Each of the 510 possible commands is defined in 2 control

registers - see Table 122 for a description of these registers.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R22

(0016h)

Write

Sequencer

Ctrl 0

WSEQ_ABORT

Writing a 1 to this bit aborts the current

sequence.

WSEQ_START

Writing a 1 to this bit starts the write

sequencer at the index location selected

by WSEQ_START_INDEX. At the end of

the sequence, this bit will be reset by the

Write Sequencer.

WSEQ_ENA

Write Sequencer Enable

0 = Disabled

1 = Enabled

Only applies to sequences triggered

using the WSEQ_START bit.

WM8281ECS/R Datenblatt(PDF) 296 Page - Cirrus Logic

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