SPEAR600 datasheet(11/97 Pages) STMICROELECTRONICS

11 / 97 page

SPEAr600

Architecture overview

Doc ID 16259 Rev 3

11/97

Architecture overview

Figure 2. shows an example of a typical SPEAr600 based system.

Figure 2.

Typical system architecture using SPEAr600

The core of the SPEAr600 is the dual ARM926EJ-S reduced instruction set computer

(RISC) processor.

It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off

between high performance and high code density and includes features for efficient

execution of Java byte codes.

Each ARM CPU:

●

Is clocked at a frequency up to 333 MHz

●

Embeds 16 Kbytes instruction cache + 16 Kbytes data cache

●

Features a memory management unit (MMU) which makes it fully compliant with Linux

and VxWorks operating systems.

The SoC includes three major subsystems logic domains which control the following

function blocks:

Configurable Cell Array Subsystem

This block contains the Reconfigurable Array Subsystem logic (RAS) made by an array of

600Kgate equivalent standard cells freely customizable by means of a few metal and via

mask layer changes during the customization process. The programmable logic allows

reducing the SoC NRE cost, the development cycle time improving the devices time to

Clock, Reset

32 kHz

30 MHz

RTC

8-Channel DMA

10 Timers / WD

8 KB Embed. SRAM

32 KB Embed. ROM

ADC

TouchScreen

ARM 926EJ

up to 333 MHz

MMU

Interrupt/

Syst controller

DDR

memory

controller

DDR2

DDR1

FSMC

EEPROM

SMI

FLASH

Debug, Trace

JTAG

ETM9

LCD

controller

USB2.0 PHY

device

USB2.0 PHY

device

I2C

Internet

Access

Phy

FIdDA

3xSSP

Uart2

Uart1

USB2.0 PHY

Host

USB2.0 PHY

Host

USB2.0 PHY

Host

USB2.0 PHY

Host

ARM 926EJ

up to 333 MHz

MMU

Interrupt/

Syst controller

3xI2S

EXPI I/f

NAND Flash

SPEAr600

RAS

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