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SPEAR600 Datenblatt(PDF) 42 Page - STMicroelectronics |
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SPEAR600 Datenblatt(HTML) 42 Page - STMicroelectronics |
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42 / 97 page ![]() Pin description SPEAr600 42/97 Doc ID 16259 Rev 3 3.3.4 Disable GMAC ctr The GMAC interface is disabled and alternatively the following features are provided: ● Two UARTs : one with extension for modem flow control and one with simplified hardware flow control ● One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user manual for more details). ● Four additional clocks programmable trough the GPT registers. Please refer to the SPEAr600 user manual (UM0510) for more details. 3.3.5 Self cfg_4 In this mode the AHB expansion interface is enabled on the PL_GPIO (83:0) pins. In this mode source clock and reset signals are provided from the external application logic. 3.3.6 Self cfg_5 In this mode the AHB expansion interface is enabled on the PL_GPIO (83:0) pins. In this mode source clock and reset signals are internally provided. 3.3.7 All processors disabled This mode configures the SoC as an I/O slave target device controlled by an external master application (the internal processors can be disabled). |
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