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STM32L021D4 Datenblatt(PDF) 27 Page - STMicroelectronics

Teilenummer STM32L021D4
Bauteilbeschribung  Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AES
PDF  114 Pages
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Hersteller  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32L021D4 Datenblatt(HTML) 27 Page - STMicroelectronics

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STM32L021x4
Functional overview
32
3.12
Ultra-low-power comparators and reference voltage
The STM32L021x4 embed two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
One comparator with ultra low consumption
One comparator with rail-to-rail inputs, fast or slow mode.
The threshold can be one of the following:
External I/O pins
Internal reference voltage (VREFINT)
submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail
comparator.
Both comparators can wake up the devices from Stop mode, and be combined into a
window comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
3.13
System configuration controller
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM21 and LPTIM1 timer input captures. It also controls the
routing of internal analog signals to the ADC, COMP1 and COMP2 and the internal
reference voltage VREFINT.
3.14
AES
The AES Hardware Accelerator can be used to encrypt and decrypt data using the AES
algorithm (compatible with FIPS PUB 197, 2001 Nov 26):
Key scheduler
Key derivation for decryption
128-bit data block processed
128-bit key length
213 clock cycles to encrypt/decrypt one 128-bit block
Electronic codebook (ECB), cypher block chaining (CBC), and counter mode (CTR)
supported by hardware.
The AES can be served by the DMA controller.



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