STM32L021D4 datasheet(30/114 Pages) STMICROELECTRONICS

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Functional overview

STM32L021x4

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DocID027982 Rev 5

3.16

Communication interfaces

3.16.1

I2C bus

One I2C interface (I2C1) can operate in multimaster or slave modes. The I2C interface can

support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to 400 kbit/s) and Fast

Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.

The I2C interface supports 7-bit and 10-bit addressing modes, multiple 7-bit slave

addresses (2 addresses, 1 with configurable mask). They also include programmable

analog and digital noise filters.

In addition, I2C1 provides hardware support for SMBus 2.0 and PMBus 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and

ALERT protocol management. I2C1 also has a clock domain independent from the CPU

clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.

The I2C interface can be served by the DMA controller.

Refer to Table 8 for the supported modes and features of I2C interface.

Table 7. Comparison of I2C analog and digital filters

Analog filter

Digital filter

Pulse width of

suppressed spikes

≥ 50 ns

Programmable length from 1 to 15

I2C peripheral clocks

Benefits

Available in Stop mode

1. Extra filtering capability vs.

standard requirements.

2. Stable length

Drawbacks

Variations depending on

temperature, voltage, process

Wakeup from Stop on address

match is not available when digital

filter is enabled.

Table 8. STM32L021x4 I2C implementation

I2C features(1)

1. X = supported.

I2C1

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

X(2)

2. See Table 12: Pin definitions on page 36 for the list of I/Os that feature Fast Mode Plus capability

Independent clock

SMBus

Wakeup from STOP

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