TLV9152 datasheet(25/45 Pages) TI

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±500 µV, which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in

15,873 units.

Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits

will be removed from production material. For example, the TLV915x-Q1 family has a maximum offset voltage

of 675 µV at 25°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely

unlikely, TI assures that any unit with larger offset than 895 µV will be removed from production material.

For specifications with no value in the minimum or maximum column, consider selecting a sigma value of

sufficient guardband for your application, and design worst-case conditions using this value. For example, the

6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an

option as a wide guardband to design a system around. In this case, the TLV915x-Q1 family does not have

a maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.3 µV/°C in

Section 6.7, it can be calculated that the 6-σ value for offset voltage drift is about 1.8 µV/°C. When designing for

worst-case system conditions, this value can be used to estimate the worst possible offset across temperature

without having an actual minimum or maximum value.

However, process variation and adjustments over time can shift typical means and standard deviations, and

unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a

device. This information should be used only to estimate the performance of a device.

7.3.9 Packages With an Exposed Thermal Pad

The TLV915x-Q1 family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which

feature an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically

conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad

must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not

allowed, and performance of the device is not assured when doing so.

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TLV9152-Q1, TLV9154-Q1

SBOSA23B – MAY 2020 – REVISED MARCH 2021

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TLV9152 Datenblatt(PDF) 25 Page - Texas Instruments