AX88141 datasheet(11/43 Pages) ASIX

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AX88141

PRELIMINARY

ASIX ELECTRONICS CORPORATION

CONFIDENTIAL

AD<31>

AD<30>

AD<29>

AD<28>

AD<27>

AD<26>

AD<25>

AD<24>

AD<23>

AD<22>

AD<21>

AD<20>

AD<19>

AD<18>

AD<17>

AD<16>

AD<15>

AD<14>

AD<13>

AD<12>

AD<11>

AD<10>

AD<9>

AD<8>

AD<7>

AD<6>

AD<5>

AD<4>

AD<3>

AD<2>

AD<1>

AD<0>

I/O

10,

11,

13,

14,

16,

17,

19,

20,

24,

25,

26,

27,

29,

30,

33,

34,

50,

51,

52,

54,

55,

57,

58,

59,

62,

63,

64,

66,

67,

69,

70,

Address and data bits are multiplexed on the same pins. During the address phase, the AD<31:0>

contain a physical address (32 bits). During, data phases, AD<31:0> contain 32 bits of data.

The AX88141 supports both read and write bursts (in master operation only). Little and big endian byte

ordering can be used.

PCI_CLK

The clock provides the timing for the AX88141 related PCI bus transactions. All the bus signals are

sampled on the rising edge of PCI_CLK. The clock frequency range is between 20MHZ and 33MHZ.

PERR#

I/O

Parity error asserts when a data parity error is detected. When the AX88141 is the bus master it monitor

PERR# to see if the target report a data parity error., when the AX88141 is the bus target and a parity

error is detected, the AX88141 asserts PERR#. This pin must be pulled up by an external resistor.

REQ#

Bus request is asserted by the AX88141 to indicate to the bus arbiter that it wants to use the bus.

RST#

Resets the AX88141 to its initial state. This signal must be asserted for at least 10 active PCI clock

cycles. When is the reset state, all PCI output pins are put into tri-state and all PCI o/d signals are

floated.

SERR#

I/O

System Error is used by AX88141 to report address parity Error. This pin must be pulled up by an

external resistor.

STOP#

I/O

Stop indicator indicates that the current target is requesting the bus master to stop the current transaction.

The AX88141 responds to the assertion of STOP# when it is the bus master, and stop the current

transaction.

TRDY#

I/O

Target ready indicates the target ability to complete the current data phase of the transaction.

A data phase is completed on any clock when both TRDY# and IRDY# are asserted. Wait cycles are

inserted until both IRDY# and TRDY# are asserted together. When the AX88141 is the bus master,

target ready is asserted by the bus slave on the read operation, indicating that valid data is present on the

ad lines. During a write cycle, it indicates that the target is prepared to accept data.

PME#

Tab - 1 PCI interface group

2.3 Boot ROM , Serial ROM , General-purpose signals group

SIGNAL

TYPE

NUMBER

DESCRIPTION

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