USB97C100QFP datasheet(27/64 Pages) SMSC

27 / 64 page

SMSC DS – USB97C100

Page 27

Rev. 01/03/2001

MCU ISA Interface Registers

Table 33 – ISA Bus Request Register

BUS_REQ

(0x7F70 – RESET=0x00)

ISA BUS REQUEST REGISTER

BIT

NAME

R/W

DESCRIPTION

INH_TC3

R/W

This bit inhibits DMA channel 3 TC.**See Note Below

0 = TC is driven onto the ISA bus via EOP as before.

1 = TC is forced inactive.

INH_TC2

R/W

This bit inhibits DMA channel 2 TC.** See Note Below

0 = TC is driven onto the ISA bus via EOP as before.

1 = TC is forced inactive.

INH_TC1

R/W

This bit inhibits DMA channel 1 TC.** See Note Below

0 = TC is driven onto the ISA bus via EOP as before.

1 = TC is forced inactive.

INH_TC0

R/W

This bit inhibits DMA channel 0 TC.** See Note Below

0 = TC is driven onto the ISA bus via EOP as before.

1 = TC is forced inactive.

RESET_8237

R/W

Writing a '1' holds the 8237 hardware reset input active. Writing

'0' releases it for normal operation. May be used for clock

switching or power management functions.

AEN

This bit reflects the status of the 8237's AEN pin. This bit does

not generate an interrupt

HLDA

R/W

The 8051 can grant the bus when it is ready via HLDA. This

should tri-state any common signals between the 8051 and the

8237 on the ISA bus.

HREQ

This bit reflects the status of the 8237's HREQ bus request pin.

This bit does not generate an interrupt.

Note:

HLDA Example: When the 8051 is running at 24MHz, and the 8237 is running at 2MHz, the 8237 may take

up to 1.5us to complete a transfer after deasserting HLDA . When running the 8051 at 24MHz, wait states

must be added when the 8237 is running at 2 or 4 MHz. When running the 8051 at 12MHz, wait states must

be added when the 8237 is running at 2 MHz.

Note**: The “Inhibit” function is not valid for Memory-to-Memory DMA cycles

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