USB97C100QFP datasheet(46/64 Pages) SMSC

46 / 64 page

SMSC DS – USB97C100

Page 46

Rev. 01/03/2001

SIE Interface Registers

The architecture of the USB97C100 is such that there are no data FIFO's associated with individual endpoints. The

MMU does not differentiate packets by endpoint number. The firmware must read the endpoint number from the

packet header to pass the packet on to the appropriate endpoint handler. This makes the chip dynamic and flexible

in allocating buffers to store any payload size from 0 to 1280 bytes. Each endpoint can be configured separately via

the following register:

Table 76 - Endpoint Control Registers

EP_CTRL[15..0]

(0x7F8F-0x7F80 - RESET=0x00)

ENDPOINT CONTROL REGISTERS

BIT

NAME

R/W

DESCRIPTION

TX_ISO

R/W

Bit 7 instructs the SIE how to handle handshakes for transmit

endpoints during "IN" transactions, and how the SIEDMA

engine should handle packet queue status after packet

transmission. When a TX endpoint is configured for

isochronous operation (Bit 7 = '1'), all packet transmissions are

considered successful and the SIEDMA must move the packet

number into the TX Completion FIFO. When the TX endpoint is

non-isochronous (Bit 7 = '0'), then the SIE must receive a valid

ACK handshake from the host before the packet is released.

This guarantees data integrity for non-isochronous

transactions.

Successfully transmitted packets are automatically de-queued

and the packet is released.

0 = Non-Isochronous

1 = Isochronous

RX_ISO

R/W

Bit 6 instructs the SIE how to handle handshakes for receive

endpoints during "OUT" and "SETUP" transactions. Once a

packet matches the 7-bit Function Address, the SIE must begin

page allocation and generate a new packet in buffer RAM. The

MCU must check PID_Valid and CRC_Valid bits and dequeue

"bad" packets. The SIE will use bit 6 to inhibit handshakes

when enabled.

0 = Non-isochronous

1 = Isochronous

5,3

TX_CONT[1:0]

R/W

0,0= Endpoint is disabled, and does not send handshakes.

0,1= Send a STALL handshake for an IN transaction directed at

this EP.

1,0= Normal Operation. ACK or NAK is sent depending on

whether data is in the EPXs TX_QUEUE.

1,1= Send a NAK handshake for an IN transaction directed at

this EP, regardless of TX_QUEUE status. (Note 3)

4,2

RX_CONT[1:0]

R/W

0,0= Endpoint is disabled, and does not send handshakes.

0,1= Send a STALL handshake for an OUT transaction directed

at this EP.

1,0= Normal Operation. ACK or NAK is sent depending on

RX_OK status

1,1= Send a NAK handshake for an OUT transaction directed

at this EP (Note 1)

TX_TOGGLE

R/W

This bit is toggled after each successful transmission.

TX_TOGGLE can be reset or cleared by the MCU but the MCU

must insure that the endpoint is disabled before modifying

them.

RX_TOGGLE

This bit reflects the last DATA0/DATA1 toggle.

Notes:

There is one Endpoint Control Register per virtual endpoint. When the SIE decodes a token, the endpoint

number is used to index which EP_CTRL register bits should be used to respond to the SIE and SIEDMA.

This register allows firmware to throttle back RX packets to any specific endpoint(s) until the firmware decides

congestion has subsided.

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