USB97C100QFP datasheet(29/64 Pages) SMSC

29 / 64 page

SMSC DS – USB97C100

Page 29

Rev. 01/03/2001

Table 35 - ISA Bus Status Mask Register

BUS_MASK

(0x7F74 - RESET=0xFF)

ISA BUS STATUS MASK REGISTER

BIT

NAME

R/W

DESCRIPTION

CH3RQ_MASK

R/W

Channel 3 DMA Request ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

CH2RQ_MASK

R/W

Channel 2 DMA Request ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

CH1RQ_MASK

R/W

Channel 1 DMA Request ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

CH0RQ_MASK

R/W

Channel 0 DMA Request ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

CH3TC_MASK

R/W

Channel 3 Terminal Count ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

CH2TC_MASK

R/W

Channel 2 Terminal Count ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

CH1TC_MASK

R/W

Channel 1 Terminal Count ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

CH0TC_MASK

R/W

Channel 0 Terminal Count ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Table 36 - ISA I/O Window Base Register

IOBASE

(0x7F71 - RESET=0x00)

ISA I/O WINDOW BASE REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:0]

SA[15:8]

R/W

When the 8051 reads or writes to the ISA I/O Window,

this register is combined with the 8 bit offset in the 256

byte window and presented as the 64k I/O Space address

during an 8051-ISA IOR or IOW cycle

Table 37 - ISA Memory Window Base Register

MEMBASE

(0x7F72 - RESET=0x00)

ISA MEMORY WINDOW BASE REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:0]

SA[19:12]

R/W

When the 8051 reads or writes to the ISA Memory

Window, this register is combined with the 12 bit

offset in the 4k byte window and presented as the

1Mbyte Memory address during an 8051-ISA

MEMR or MEMW cycle.

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