USB97C100QFP datasheet(36/64 Pages) SMSC

36 / 64 page

SMSC DS – USB97C100

Page 36

Rev. 01/03/2001

Table 55 - Read Temporary Register

RD_TEMP

(ISA 0x000D)

READ TEMPORARY REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:0]

TEMP_BYTE

This location holds the value of the last byte transferred in a

memory-to-memory operation.

Table 56 - Master Clear Register

MSTR_CLR: (ISA 0x000D)

MASTER CLEAR REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:0]

SW_RESET

Writing to this register has the same effect on the registers

as a hardware reset. The 8237 will enter the idle state.

Table 57 - Clear Mask Register

CLR_MASK: (ISA 0x000E)

CLEAR MASK REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:0]

CLR_ALL

Writing to this register clears the mask bits of all four

channels and allows them to receive DMA requests.

Table 58 - Clear All Mask Bits Register

ALL_MASK

(ISA 0x000F)

WRITE ALL MASK BITS REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:4]

Reserved

CH3_MASK

Channel 3 Mask Bit (1 = Set Mask, 0 = Clear Mask)

CH2_MASK

Channel 2 Mask Bit (1 = Set Mask, 0 = Clear Mask)

CH1_MASK

Channel 1 Mask Bit (1 = Set Mask, 0 = Clear Mask)

CH0_MASK

Channel 0 Mask Bit (1 = Set Mask, 0 = Clear Mask)

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