USB97C100QFP datasheet(34/64 Pages) SMSC

34 / 64 page

SMSC DS – USB97C100

Page 34

Rev. 01/03/2001

Table 49 - Channel Status Register

CH_STAT

(ISA 0x0008)

CHANNEL STATUS REGISTER

BIT

NAME

R/W

DESCRIPTION

CH3RQ

Channel 3 DMA Request

0 = No Request Pending

1 = Yes Request Pending

CH2RQ

Channel 2 DMA Request

0 = No Request Pending

1 = Yes Request Pending

CH1RQ

Channel 1 DMA Request

0 = No Request Pending

1 = Yes Request Pending

CH0RQ

Channel 0 DMA Request

0 = No Request Pending

1 = Yes Request Pending

CH3TC

Channel 3 Terminal Count Reached

0 = No

1 = Yes

CH2TC

Channel 2 Terminal Count Reached

0 = No

1 = Yes

CH1TC

Channel 1 Terminal Count Reached

0 = No

1 = Yes

CH0TC

Channel 0 Terminal Count Reached

0 = No

1 = Yes

Notes:

These bits are also visible outside of I/O space in the BUS_STAT register.

These bits are cleared when this register is read through the ISA I/O Window.

Table 50 - 8237 Command Register

CH_CMD

(ISA 0x0008)

COMMAND REGISTER

BIT

NAME

R/W

DESCRIPTION

DACK_SENS

DACK Sense

0 = Active High

1 = Active Low

DREQ_SENS

DREQ Sense (1 = Active Low, 0 = Active High)

WRITE_TIME

Write Timing Select

0 = Late Timing

1 = Extended

PRIORITY

Priority

0 = Fixed

1 = Rotating

COMP_TIME

Timing

0 = Normal

1 = Compressed

CTRL_EN

Controller Enable

0 = Enable

1 = Disable

ADDR_HOLD

Channel 0 Address Hold

0 = Disable

1 = Hold Enable

MEM2MEM

Memory-to-Memory

0 = Disable

1 = Enable

USB97C100QFP Datenblatt(PDF) 34 Page - SMSC Corporation

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