USB97C100QFP datasheet(38/64 Pages) SMSC

38 / 64 page

SMSC DS – USB97C100

Page 38

Rev. 01/03/2001

Table 61 - Pointer Register (High)

PRH

(0x7F51)

POINTER REGISTER (HIGH)

BIT

NAME

R/W

DESCRIPTION

RCV

R/W

0 = The packet at 0x6000 is the packet pointed to by the PNR

1 = The packet available at 0x6000 is the packet pointed to by the

packet on the top of the RX Packet Number FIFO.

AUTO_INCR

R/W

0 = Auto-increment is disabled

1 = Causes the PRH:PRL register to be automatically

incremented each time the 0x6000 data window is accessed.

READ

R/W

Data register direction. This bit is required for the MMU/Arbiter to

provide a transparent interface to the buffer RAM for the MCU.

When first set, the MMU immediately fills the read FIFO. The

MCU must wait 2.5us (60 Arbiter clocks) after writing to the

MMU_DATA register before changing this bit from '0' to '1'.

0 = WRITE

1 = READ

[4:3]

Reserved

[2:0]

A[10:8]

R/W

MSB of the (0-1277 Max) offset of the allocated Packet Pointed to

by PNR. The byte(s) pointed to by this register can be read and

written to by the MCU at 0x6000.

Note: This register must be written after PRL for its value to take effect.

Table 62 - Transmit FIFO Select Register

MMUTX_SEL

(0x7F52)

TRANSMIT FIFO SELECT REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:4]

Reserved

[3:0]

EP[3:0]

R/W

This register selects which Endpoint Commands "110" and "111"

will affect when issued to the MMU

Note:

This register must be written before writing the “Enqueue Packet into Endpoint x” or the “Reset TX Endpoint

x” command to the MMUCR .

Table 63 - MMU Command Register

MMUCR

(0x7F53)

MMU COMMAND REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:5]

MMU_CMD

MMUCR COMMAND SET

Reserved

Reserved, writes are ignored and read return “0”

[3:0]

N[3:0]

Number of 128 byte Pages. N[3..0]=0000 indicates 1 page, and

N[3..0]=1001 indicates 10 pages, or 1280 bytes.

MMU COMMAND Bits 7, 6, and 5 Description:

000

NOOP, No operation

001

Allocate Memory : N3-0 specify how many 128 byte pages to allocate for that packet (up to 10

pages allowed (1280 bytes) per packet.) Immediately generates a "FAILED" code at the ARR

and the code is cleared when complete. Can generate an ALLOC interrupt to MCU upon

completion. When an allocation request cannot be completed due to insufficient memory, the

FAILED bit in the ARR will remain set. Any subsequent release of memory pages (by either

the MMUCR or the SIEDMA) will cause the MMUCR to automatically continue the allocate

command until all requested pages have been successfully allocated. Software should never

issue another allocate command until the previous allocate command has been successfully

completed.

010

RESET MMU : Frees all buffer RAM, clears interrupts, and resets queue pointers.

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