SC475AEVB datasheet(10/27 Pages) SEMTECH

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SC475A

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POWER MANAGEMENT

Zero Cross detector, then both DH and DL will remain low

until FB drops to the 0.75V reference, at which point the

next DH on-time will begin. This is normal operation at

light load.

The typical operating frequency is 325kHz. It is possible to

raise the frequency by placing a resistor divider between

the output and the VOUT pin, see Figure 2. This reduces

the voltage at the VOUT pin which is used to generate the

on-time according to the previous equation. Note that

this places a small minimum load on the output. The new

frequency is approximated by the following equation:

FREQ (kHz) = 325 ∙ (1 + R1/R2)

COUT

ESR

VOUT

VLX

pin 10

(VOUT)

1nF

Power Output

Figure 2

It is also possible to lower the frequency using a resistive

divider to the 5V bias supply, see Figure 3. This raises the

voltage at the VOUT pin which will increase the on-time.

Note that this results in a small leakage path from the 5V

supply to the output voltage. The resistor values should be

fairly large (>50kOhm) large to prevent the output voltage

from drifting up during shutdown conditions. Note that

the feedback resistors act as a dummy load to limit how

far the output can rise.

The new operating frequency is approximated by the

equation:

FREQ (kHz) = 325 ∙ ((R1 + R2) / (R1 + R2 ∙ V

CC/VOUT))

COUT

ESR

VOUT

VLX

pin 10

(VOUT)

1nF

Power Output

VCC

Figure 3

VOUT Voltage Selection

Output voltage is regulated by comparing VOUT as seen

through a resistor divider to the internal 0.75V reference,

see Figure 1. With D0 in the open state, the output voltage

is at the lowest value and is set by the equation:

OUT = 0.75 • (1 + R1/R2)

Voltage Transition Control

The SC475A provides a G0 control input to allow selecting

between two output voltages. The output voltage is regu-

lated by comparing the FB pin (connected to VOUT via an

external resistor divider) to the internal 0.75V reference.

The G0 input controls the gate of an internal MOSFET whose

source is connected to D0. Using G0 the user controls

whether D0 is grounded or open, which then controls the

resistor divider ratio for VOUT. A logic low signal on G0 will

connect D0 to ground.

When the G0 input changes state, this change quickly

causes three actions:

D0 changes state.

The power good PGD output is temporarily latched into its

present state. This prevents chattering or false tripping

while VOUT moves to the new level.

The output over-voltage OVP point is raised to 50% above

nominal, or 1.125V at FB. When going from a higher to

lower voltage, the G0 change causes rapid change of D0,

which in turns cause a rapid change at FB. The temporary

increase in OVP allows the output to slew down to the new

level without tripping the OVP function.

Applications Information (continued)

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