SC475AEVB datasheet(19/27 Pages) SEMTECH

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SC475A

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POWER MANAGEMENT

divider network, as shown in Figure 13. This capacitance

should be left out until conﬁrmation that double-pulsing

exists. Adding this capacitance will add a zero in the

transfer function and should eliminate the problem. It is

best to leave a spot on the PCB in case it is needed.

TON

0.75V

SC475A

VOUT

Logic

Control

Figure 13

Loop instability can cause oscillations at the output as a

response to line or load transients. These oscillations can

trip the over-voltage protection latch or cause the output

voltage to fall below the tolerance limit.

The best way for checking stability is to apply a zero-to-

full load transient and observe the output voltage ripple

envelope for overshoot and ringing. Over one cycle of

ringing after the initial step is a sign that the ESR should

be increased.

SC475A ESR Requirements

The constant on-time control used in the SC475A

regulates the valley of the output ripple voltage. This

signal consists of a term generated by the output ESR of

the capacitor and a term based on the increase in voltage

across the capacitor due to charging and discharging

during the switching cycle. The minimum ESR is set to

generate the required ripple voltage for regulation. For

most applications the minimum ESR ripple voltage is

dominated by PCB layout and the properties of SP or

POSCAP type output capacitors. For applications using

ceramic output capacitors, the absolute minimum ESR

must be considered. If the ESR is low enough the ripple

voltage is dominated by the charging of the output

capacitor. This ripple voltage lags the on-time due to the

LC poles and can cause double pulsing if the phase delay

exceeds the off-time of the converter. To prevent double

pulsing, the ripple voltage present at the FB pin should be

10-15mV minimum over the on-time interval.

Dropout Performance

The VOUT adjust range for continuous-conduction

operation is limited by the ﬁxed 350nsec (typical) Minimum

Off-time One-shot. When working with low input voltages,

the duty-factor limit must be calculated using worst-case

values for on and off times.

The IC duty-factor limitation is given by:

DUTY = TONMIN/(TONMIN + TOFFMAX)

Be sure to include inductor resistance and MOSFET on-

state voltage drops when performing worst-case dropout

duty-factor calculations.

SC475A System DC Accuracy (VOUT Controller)

Three factors affect VOUT accuracy: the trip point of the

FB error comparator, the switching frequency variation

with line and load, and the external resistor tolerance.

The error comparator offset is trimmed to trip when the

feedback pin is 0.75V, +/-1%.

The on-time pulse in the SC475A is calculated to give a

pseudo-ﬁxed frequency of 325kHz. Nevertheless, some

frequency variation with line and load is expected. This

variation changes the output ripple voltage. Because

constant on-time converters regulate to the valley of

the output ripple, ½ of the output ripple appears as a

DC regulation error. For example, If the output ripple is

50mV with VIN = 6 volts, then the measured DC output

will be 25mV above the comparator trip point. If the ripple

increases to 80mV with VIN = 25 volts, then the measured

DC output will be 40mV above the comparator trip. The

best way to minimize this effect is to minimize the output

ripple.

To compensate for valley regulation it is often desirable

to use passive droop. Take the feedback directly from the

output side of the inductor, placing a small amount of trace

resistance between the inductor and output capacitor.

This trace resistance should be optimized so that at full

load the output droops to near the lower regulation limit.

Applications Information (continued)

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