SC475AEVB datasheet(12/27 Pages) SEMTECH

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SC475A

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POWER MANAGEMENT

Note that at light loads it can take many msec for the

output to fall to the new value. This should have no

adverse effect. Many loads such as graphics chipsets

can have a minimum load of several hundred mA, which

will naturally pull VOUT down to the next level.

750mV

VOUT

RTN

< 810mV

(FB threshold)

COUT Discharge due to load

Initial

VOUT

Final

VOUT

(Smart Psave threshold)

Figure 6

For the case in Figure 6 the time needed to reach the ﬁnal

voltage is found from the following equation, where COUT

is in μF, and LOAD is in Amps:

Time (μsec) = COUT * (V

INITIAL – VFINAL)/LOAD

Note that the above equation only applies to the condition

where the VOUT downward change is less that the 8%

limit for Smart Psave, and also the load is light such that

Psave is active.

When doing an up transition (from lower to higher VOUT),

the G0 change affects D0 and causes FB to drop below

the 0.75V trip point. This quickly trips the FB comparator

regardless of whether psave is active or not, generating a

DH on-time and a subsequent DL high time. At the end

of the minimum off-time (350nsec), if FB is still below

0.75V then another DH on-time is started. This sequence

continues until the FB pin exceeds 0.75V see Figure 7.

VOUT

RTN

750mV

(FB threshold)

VOUT

Final

VOUT

Initial

VOUT

Figure 7

If the VOUT change is signiﬁcant, there can be several

consecutive cycles of DH on-time followed by minimum DL

time. This can cause a rapid increase in inductor current:

typically it only takes a few switching cycles for the induc-

tor current to rise up to the Current Limit. At some point

the FB voltage will rise up to the 0.75V reference and the

DH pulses will cease, but the inductor’s LI2 energy must

then ﬂow into the output cap. This can create a signiﬁcant

overshoot as shown in Figure 8.

Applications Information (continued)

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