ACT4921 datasheet(20/35 Pages) QORVO

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Data Sheet Rev. B, January 2020 | Subject to change without notice

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ACT4921

Power Loss Protection with 6A eFuse

Table 4: Over Voltage Reference Settings

VINS_OV_REF[2:0]

OV Threshold (V)

000

Disabled

001

0.82

010

0.92

011

1.00

100

1.08

101

1.16

110

1.24

111

1.32

ENB

The ENB pin enables the blocking FET, the buck

converter, and the boost converter. They are disabled

when ENB is low and enabled when ENB is high. ENB

provides two main system level functions. The first is to

isolate the storage capacitors as startup to allow faster

system startup. ENB is typically held low by the system

processor at startup. After the system starts up, the

processor pulls ENB high to allow the boost converter

to charge the storage caps. The second function is to

provide fault isolation. In the event of a storage

capacitor failure, ENB can be pulled low to isolate the

capacitors from the system. This allows the system to

continue operating until it can be safely shutdown.

STR

STR is the output to the storage capacitor bank. In

normal operation the internal boost converter charges

the storage capacitors through the STR pin. When the

IC enters supplement mode, the internal buck converter

uses the STR pin as its input to power the system. The

STR pin is typically connected to hundreds of

microfarads of storage capacitance. It always requires

a 22uF or greater ceramic capacitor. See the Buck

Converter section for more information.

nIRQ—Interrupt

ACT4921 has an interrupt pin to inform the host of any

fault conditions. In general, any IC function with a status

bit asserts nIRQ pin low if the status changes. The

status changes can be masked by setting their

corresponding register bits. If nIRQ is asserted low, the

fault must be read before the IC deasserts nIRQ. If the

fault remains after reading the status bits, nIRQ remains

asserted.

The status changes shown below assert the nIRQ pin:

•

Input overvoltage, undervoltage

•

Thermal warning, thermal shutdown

•

eFuse VIN to VOUT over limits

•

eFuse current warning and limit

•

VB pin is not valid (VB or STR short)

•

Storage capacitor overvoltage, undervoltage

•

Supplemental mode active

•

Buck operation faults

•

Buck undervoltage shutdown

•

REF LDO undervoltage

nIRQ is an open-drain output and should be pulled up

to an appropriate supply voltage with a 10kΩ or greater

pull-up resistor.

SCL, SDA

SCL and SDA are the I2C clock and data pins to the IC

They have standard I2C functionality. They are open-

drain outputs and each require a pull-up resistor. The

pull-up resistor is typically tied to the system’s uP IO

pins. The pullup voltage can range from 1.8V to 5.0V.

REF

The REF pin is an internal bias voltage output pin.

Connect a 1µF capacitor between REF and AGND. Do

not apply an external load to the REF pin.

BSET

BSET sets the boost converter output voltage. The

output voltage is a function of both a resistor connected

between BSET and AGND as well as internal I2C

section for more information.

ISET

ISET sets the eFuse current limit with a resistor

connected to AGND. See the eFuse section for more

information.

The SS pin uses a capacitor to AGND to control the

eFuse softstart timing. See the eFuse section for more

information.

PGND

The PGND pin is the buck and boost converters’ power

ground. The internal FETs connect directly to the PGND

pins. The power supply input and output capacitors

should connect to the PGND pins.

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