ACT4921 datasheet(21/35 Pages) QORVO

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Data Sheet Rev. B, January 2020 | Subject to change without notice

21 of 35

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ACT4921

Power Loss Protection with 6A eFuse

AGND

The AGND pin is the IC’s analog ground pin. It is a “quiet”

ground pin that is separate and isolated from the high

power, high current carrying PGND ground plane.

Connect the non-power components to AGND. AGND

must be kelvin connected to the PGND pin in a single

location.

COMP

COMP is the output of a transconductance amplifier that

is used to compensate the internal buck converter. The

compensation components, which are typically a

standard type-2 compensation should be grounded to

the AGND pin. See the Application section for more

information

compensating

the

internal

buck

converter.

PLI

PLI (Power Loss Indicator) goes high after softstart and

stays high in normal operation. PLI immediately goes

low when the IC enters supplement mode. This setting

is used to let the system uP know that power loss is

imminent.

The PLI pin is an open-drain output and is 5V compliant.

The FB pin is used to regulate the buck converter output

voltage when the IC is in supplement mode.

HSB

HSB provides power to the internal high-side MOSFET

gate driver circuitry. Connect a 47nF capacitor from

HSB pin to SW pin.

SW is the switch node for the internal buck and boost

converters. Connect the inductor to the SW pin.

VOUT

VOUT is the output of the eFuse and connects to the

system load. The eFuse connects VOUT to VIN in

normal operation, and it disconnects it in supplement

mode.

VB is the output pin from the blocking FET. Depending

on the operating mode, power either flows into or out of

VB. In normal operation, power flows from VIN, through

the eFuse and blocking FETs and out of VB to provide

input power to the boost converter. ENB must be pulled

high to enable this functionality.

During supplement mode, the buck converter output

power flows into VB, through the blocking FET, and out

of VOUT to the system.

DISCHG

DISCHG is the discharge pin for the storage capacitors.

When the IC enters the UV/POR state, DISCHG is

internally connected to PGND through an internal FET.

Connect a resistor between DISCHG and STR to

quickly discharge the storage capacitance. The user

can manually turn on the DISCHG FET by setting the

DISCHG_STR bit to 1.

The discharge function is typically only used during

product development and evaluation. It allows the user

to quickly discharge large storage capacitor values

between testing to ensure the next power cycle starts

with discharged capacitors. If the function is not used in

production, the discharge resistor can be removed from

the board and the DISCHG pin can be connected to

PGND or left open. The discharge resistor should be

chosen to keep the discharge current less than 100mA.

PG_STR

PG_STR is a power good indicator for the storage

capacitors. It goes high when the storage capacitor

voltage goes into regulation. It goes low when the

voltage drops below 95% of the setpoint. It also goes

low when either the buck or boost converter is disabled.

It is open drain and is 5V compliant.

PG_VO

PG_VO is a power good indicator for VOUT. It goes high

when the eFuse is fully turned on. In supplement mode,

it starts high and then goes low when the FB pin drops

below 95% of VFB_REF (0.8V). It is open drain and is 5V

compliant.

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