ACT4921 datasheet(24/35 Pages) QORVO

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Data Sheet Rev. B, January 2020 | Subject to change without notice

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ACT4921

Power Loss Protection with 6A eFuse

Frequency Setting

Higher switching frequencies result in smaller solution

sizes at the cost of slightly lower efficiency. Lower

switching frequencies result in larger solution sizes with

higher efficiency. The

following

table

gives

the

maximum allowable switching frequency as a function

of storage voltage.

Table 5: Maximum Allowable Buck Switching

Frequency

Storage Voltage

Maximum Buck Switching

Frequency

< 18V

2.25MHz

18V to 25V

1.5MHz

> 25V to 28V

1.125MHz

Output Voltage Setting

The buck converter output voltage is programmed by an

external resistor divider connected between the VB pin

and AGND, with the center tap connected to the FB pin.

The buck output voltage can be set above, below, or

equal to the input voltage supplement threshold. When

the input voltage goes outside the normal operating

voltage set by the VINS pin, the IC enters supplement

mode and regulates the output voltage to the

programmed buck voltage. Although the buck converter

immediately starts up when the IC enters supplement

mode, the output voltage still has a small, but finite drop

in output voltage between the time the eFuse turns off

and the buck converter is fully on. This voltage drop

should be considered when setting the output voltage.

The following equation calculates the correct resistor

values to set the desired output voltage.

2 &

' − 1)

(5)

Where R1 is the top feedback resistor, R2 is the bottom

feedback resistor, VBUCK is the desired output voltage,

and VFB is the fixed 0.8V reference voltage on the FB

pin. Choose R2 in the range of 10kohm. Smaller resistor

values are acceptable, but larger values will affect

voltage accuracy due to bias currents into the FB pin.

Protection

The buck converter has several protection mechanisms

to insure safe operation. It stops operation when input

voltage from storage cap drops below STR_UVLO

(3.0V) or when the output voltage drops below the

power good threshold which is fixed at 93% of the

output setpoint. Note that the output undervoltage

protection is masked by default, but can be unmasked

by the I2C register bit Mask_BK_UV REG0x11 [0].

The buck converter provides overcurrent and short

circuit protection. Overcurrent protection is achieved

with cycle-by-cycle current limiting. The peak current

threshold is set to either 6A or 10A by BKILIM_OPT. If

the peak current reaches the programmed threshold,

the IC turns off the power FET. This condition typically

results in shutdown due to an output voltage UV

condition due to the shortened switching cycle.

A short circuit condition that results in the peak switch

current being 122.5% of BKILIM_OPT immediately

shuts down the supply and asserts nIRQ low. A buck

overcurrent, undervoltage, or overvoltage condition

moves the IC into the UV/POR state.

Compensation

The

Buck

regulator

utilizes

type

external

compensation placed on the COMP pin. Contact the

factory for compensation details.

Input Capacitor Selection

The STR pin is the input voltage to the buck converter.

It requires a dedicated high quality, low-ESR, ceramic

input capacitor that is optimally placed to minimize the

power routing. For optimal PCB layout considerations,

1206 or 1210 sized input capacitors are recommended.

A 22uF capacitor is typically suitable, but the actual

value is application dependent. The input capacitor can

be increased without limit. Choose the input capacitor

value to keep the input voltage ripple less than 50mV

' +,

.1 − ' +,

- /

1 223

(6)

Where Iout is the maximum eFuse load current in

Amperes, VSTR is the maximum storage voltage, VBUCK

is the buck output voltage, FSW is the switching

frequency, and Vripple is the maximum allowable ripple

voltage on the input of the buck converter. Note that the

storage capacitor values should not be considered

when calculating the input voltage ripple because they

are

not

typically

designed

for

high

frequency

functionality.

Be sure to consider the input capacitor’s DC bias effects.

A capacitor’s actual capacitance is strongly affected by

its DC bias characteristics. The input capacitor is

typically an X5R, X7R, or similar dielectric. Use of Y5U,

Z5U, or similar dielectrics is not recommended. Input

capacitor placement is critical for proper operation. The

buck’s input capacitor must be placed as close to the IC

as possible. The traces from STR to the capacitor and

from the capacitor to PGND should as short and wide

as possible.

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