Data Sheet Rev. B, January 2020 | Subject to change without notice

5 of 35

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ACT4921

Power Loss Protection with 6A eFuse

PIN DESCRIPTIONS

PIN

NAME

DESCRIPTION

1

HSB

High Side Bias, Boot-strap pin. This provides power to the internal high-side MOSFET gate driver

circuitry. Connect a 47nF capacitor from HSB pin to SW pin

2

STR

Storage Capacitor Input. Connect the storage capacitors to STR. STR requires a minimum capacitor

of 100µF to PGND.

3

PG_STR

Power Good Indicator Open-Drain Output for storage capacitor. Storage capacitor voltage is good

when high, and pulls low when the storage voltage falls below 95% of the nominal voltage setting or

when Buck and Boost circuits are disabled. This pin is referenced to AGND

4

PLI

Power Loss Indicator Open-Drain Output for VIN. PLI goes high when the eFuse is turned on and

goes low when the IC enters supplement mode. PLI is referenced to AGND.

5

PG_VO

Power Good indicator Open-Drain for Vout. PG_VO goes high when the eFuse is fully turned on, and

pulls low when the FB voltage falls below 95% of VFB_REF in supplement mode. PG_VO is referenced

to AGND

6

FB

Output Voltage Feedback. Kelvin connect FB to the output capacitor.

7

COMP

Compensation input pin for the buck converter.

8

REF

Internal Bias Voltage Output. Connect a 1µF capacitor between REF and AGND.

9,10,29

PGND

Power Ground. Connect to large ground plane on PCB

11

SCL

I2C Clock Input. Needs an external pull up resistor.

12

SDA

I2C Data Input and Output. Needs an external pull up resistor.

13

nIRQ

Interrupt Open-Drain Output. nIRQ goes low to indicate a fault condition. nIRQ is referenced to AGND.

14

ENB

Boost circuit & blocking FET enable signal. Pulled high internally. When it is pulled to AGND, Boost

and Buck circuit is disabled, and blocking FET is OFF.

15,16

AGND

Analog Ground. Kelvin connect AGND to the PGND plane.

17

EN

Enable Input. This is a digital enable signal for the IC. Pulled high internally. When high, the eFuse

turn on. When it is pulled to AGND, eFuse turns off, the IC goes into supplement mode, and stays in

HIZ mode after supplement mode ends.

18

SS

Soft Start Input. Place a capacitor from SS to VSS to control the eFuse startup voltage slew rate.

19

BSET

Sets the storage capacitor’s boosted output voltage. Place a resistor from BSET to AGND to set the

desired voltage.

20

ISET

Input Current Limit pin. Connect a resistor from ISET to AGND to set the current limit. ISET can also

be monitored to measure the eFuse current.

21

VINS

Input Voltage Sense for Under Voltage and Over Voltage faults. A dual comparator on VINS

measures the input voltage to determine if it is under, voltage, over voltage, or within normal operating

limits. Connect a resistive voltage divider to VINS to set the UV and OV limits. The UV threshold is

0.64V. The OV threshold is set by the IC’s specific CMI. VINS is referenced to AGND

22,23,24

VIN

Power Supply Input. Input to the eFuse. Connect a 0.1µF capacitor between VIN and PGND as close

to the IC as possible.

25,26,27,35

VOUT

Output for by-pass mode, in-rush, and eFuse functionality. Connect VOUT to the system load.

28,34

VB

Buck circuit output and Boost circuit input pin. It is isolated from VOUT with the internal blocking FET.

Place the inductor between VB and SW.

30

DISCH

Storage Cap Discharge pin. Connect a resistor between DISCHG and STR to quickly discharge the

storage caps whenever device enters the POR/UV state or when user forces STR to discharge by

setting the DISCHG_STR[ ] bit.

31,32,33

SW

Switching Pin. This is the boost converter switch node and the buck converter switch node. Connect

the inductor to SW.

Exposed Pad

PGND

Power Ground. Connect to large ground plane on PCB with thermal vias.