ADE9178 datasheet(117/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 117 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

is not in a swell condition, as

calculated by RMSHALF.

CISWELLHALF

Phase C Current Swell

Condition Detected. Set this bit

to enable an interrupt when the

phase C current is in the swell

condition and is zero when it

is not in a swell condition, as

calculated by RMSHALF.

0x0

R/W

CVSWELLHALF

Phase C Voltage Swell

Condition Detected. Set this bit

to enable an interrupt when the

phase C voltage is in the swell

condition and is zero when it

is not in a swell condition, as

calculated by RMSHALF.

0x0

R/W

BISWELLHALF

Phase B Current Swell

Condition Detected. Set this bit

to enable an interrupt when the

phase B current is in the swell

condition and is zero when it

is not in a swell condition, as

calculated by RMSHALF.

0x0

R/W

BVSWELLHALF

Phase B Voltage Swell

Condition Detected. Set this bit

to enable an interrupt when the

phase B voltage is in the swell

condition and is zero when it

is not in a swell condition, as

calculated by RMSHALF.

0x0

R/W

AISWELLHALF

Phase A Current Swell

Condition Detected. Set this bit

to enable an interrupt when the

phase A current is in the swell

condition and is zero when it

is not in a swell condition, as

calculated by RMSHALF.

0x0

R/W

AVSWELLHALF

Phase A Voltage Swell

Condition Detected. Set this bit

to enable an interrupt when the

phase A voltage is in the swell

condition and is zero when it

is not in a swell condition, as

calculated by RMSHALF.

0x0

R/W

AUX5DIPHALF

Auxiliary 5 Channel Dip

Condition Detected. Set this bit

to enable an interrupt when the

AUX5 channel is in the dip

condition and is zero when it

is not in a dip condition, as

calculated by RMSHALF.

0x0

R/W

AUX4DIPHALF

Auxiliary 4 Channel Dip

Condition Detected. Set this bit

to enable an interrupt when the

AUX4 channel is in the dip

condition and is zero when it

0x0

R/W

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