ADE9178 datasheet(120/122 Pages) AD

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Data Sheet

ADE9178

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Rev. A | 120 of 122

Table 34. ADE9178 Register Details (Continued)

Addr

Name

Bits

Bit Name

Settings

Description

Reset

Access

when one or more bits of

STATUS2 register of ADC1 are

set.

ADC1_STATUS1

ADC1 STATUS1 Bit Mask. Set

this bit to enable an interrupt

when one or more bits of

STATUS1 register of ADC1 are

set.

0x1

R/W

ADC1_STATUS0

ADC1 STATUS0 Bit Mask. Set

this bit to enable an interrupt

when one or more bits of

STATUS0 register of ADC1 are

set.

0x1

R/W

ADC0_STATUS2

ADC0 STATUS2 Bit Mask. Set

this bit to enable an interrupt

when one or more bits of

STATUS2 register of ADC0 are

set.

0x1

R/W

ADC0_STATUS1

ADC0 STATUS1 Bit Mask. Set

this bit to enable an interrupt

when one or more bits of

STATUS1 register of ADC0 are

set.

0x1

R/W

ADC0_STATUS0

ADC0 STATUS0 Bit Mask. Set

this bit to enable an interrupt

when one or more bits of

STATUS0 register of ADC0 are

set.

0x1

R/W

DREADY_FREQ_ERROR

ADC Data Ready Frequency

Error Bit Mask. Set this bit to

enable an interrupt when ADC

Data Ready frequency is not

4KHz.

0x1

R/W

ERROR5

Error5 Bit Mask. Set this bit

to enable an interrupt when an

internal error occurs.

0x1

R/W

ADC_CRC_ERROR

ADC CRC Error Bit Mask. Set

this bit to enable an interrupt

when ADC CRC error occurs.

0x1

R/W

ERROR4

Error4 Bit Mask. Set this bit

to enable an interrupt when an

internal error occurs.

0x1

R/W

ERROR3

Error3 Bit Mask. Set this bit

to enable an interrupt when an

internal error occurs.

0x1

R/W

ERROR2

Error2 Bit Mask. Set this bit

to enable an interrupt when an

internal error occurs.

0x1

R/W

ERROR1

Error1 Bit Mask. Set this bit

to enable an interrupt when an

internal error occurs.

0x1

R/W

ERROR0

Error0 Bit Mask. Set this bit

to enable an interrupt when an

internal error occurs.

0x1

R/W

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