Data Sheet

ADRF5060

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 7 of 16

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDD

Positive Supply Voltage. See Figure 6 for the interface schematic.

2, 3, 5, 9, 10, 12, 13, 15, 16,

17, 18, 20, 21, 22, 23, 25, 26,

28, 29

GND

Grounds.

4

RFIN

RF Input. The RFIN pin is DC-coupled to 0V. No DC-blocking capacitor is necessary when the RF line potential is equal to

0V DC. See Figure 4 for the interface schematic.

6

V1

Digital Control Input 1. See Figure 5 for the interface schematic.

7

V2

Digital Control Input 2. See Figure 5 for the interface schematic.

8

XC

Digital Control Input for Cross Port Selection. See Figure 8 for the interface schematic and the Theory of Operation section

for further details.

11

OUTB

Output Path for External Path B. The OUTB pin is DC-coupled to 0V. No DC-blocking capacitor is necessary when the RF

line potential is equal to 0V DC. See Figure 4 for the interface schematic.

14

INB

Input Path for External Path B. The INB pin is DC-coupled to 0V. No DC-blocking capacitor is necessary when the RF line

potential is equal to 0 VDC. See Figure 4 for the interface schematic.

19

RFOUT

RF Output. The RFOUT pin is DC-coupled to 0V. No DC-blocking capacitor is necessary when the RF line potential is equal

to 0 VDC. See Figure 4 for the interface schematic.

24

INA

Input Path for External Path A. The INA pin is DC-coupled to 0V. No DC-blocking capacitor is necessary when the RF line

potential is equal to 0 VDC. See Figure 4 for the interface schematic.

27

OUTA

Output Path for External Path A. The OUTA pin is DC-coupled to 0V. No DC-blocking capacitor is necessary when the RF

line potential is equal to 0V DC. See Figure 4 for the interface schematic.

30

VSS

Negative Supply Voltage. See Figure 7 for the interface schematic.

EP

Exposed Pad. The exposed pad must be connected to the RF and DC ground of the PCB.