Data Sheet

ADRF5060

THEORY OF OPERATION

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The ADRF5060 integrates a driver to perform logic functions inter-

nally and to provide the user with the advantage of a simplified

CMOS-/LVTTL-compatible control interface. The driver features dig-

ital control input pins (XC, V1, and V2) that control the state of the

external paths.

RF INPUT AND OUTPUT

All of the RF ports are DC-coupled to 0V, and no DC blocking

capacitor is required at the RF ports if the RF line potential is equal

to 0V.

The RF ports are internally matched to 50Ω; therefore, external

matching networks are not required.

The insertion loss path conducts the RF signal between the se-

lected RF path and the RFIN or RFOUT port. The through path

conducts RF signal between the RFIN to RFOUT pins. The isolation

path provides high loss between the insertion loss path and the

unselected RF port that is terminated to an internal 50Ω resistor.

The XC pin is used for the selection cross connections between

External Path A or External Path B (see Table 6).

The switch design is bidirectional with equal power handling capa-

bilities. The RF input signal can be applied to the RFIN or RFOUT

ports or the External A or External B paths.

Figure 23. External Path A (Left) and External Path B (Right) Configuration

Figure 24. Through (Left) and All Off (Right) Configuration

Figure 25. XC Configurations OUTB and INA (Left) or OUTA and INB (Right)

Table 6. Control Voltage Truth Table

RF Path Selection

XC

V1

V2

Through

Don't care

Low

Low

External Path B

Low

Low

High

External Path A

Low

High

Low

All Off (Isolation)

Don't care

High

High

Through

Don't care

Low

Low

Out A and In B

High

Low

High

Out B and In A

High

High

Low

All Off (Isolation)

Don't care

High

High

POWER SUPPLY

The ADRF5060 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD and VSS voltages. Power up VSS after VDD to

avoid current transients on VDD during ramp up.

3. Apply the digital control input (XC, V1, and V2). The relative

order of the control inputs is not important. However, applying

the digital control input pins before the VDD supply can inadver-

tently forward bias and damage the internal ESD protection

structures. A series 1kΩ resistor can be used to limit the current

flowing into the digital control input pins in such cases. If the

digital control input pins are not driven to a valid logic state

(that is, the controller output is in a high impedance state)

after VDD is powered up, it is recommended to use pull-up and

power-down resistors.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.