ADS5500IPAPR datasheet(22/37 Pages) TI2

22 / 37 page

www.ti.com

APPLICATION INFORMATION

THEORY OF OPERATION

INPUT CONFIGURATION

ADS5500

SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007

clock cycle. This process results in a data latency of

17.5 clock cycles, after which the output data is

available as a 14-bit parallel word, coded in either

The ADS5500 is a low-power, 14-bit, 125 Msps,

straight offset binary or binary two's complement

CMOS,

switched

capacitor,

pipeline

ADC

that

format.e sample through the pipeline every half clock

operates from a single 3.3-V supply. The conversion

cycle. This process results

process is initiated by a falling edge of the external

input clock. Once the signal is captured by the input

S&H, the input sample is sequentially converted by a

series of small resolution stages, with the outputs

The analog input for the ADS5500 consists of a

combined in a digital correction logic block. Both the

differential

sample-and-hold

architecture

rising and the falling clock edges are used to

implemented using a switched capacitor technique,

propagate the sample through the pipeline every half

shown in Figure 41.

NOTE: All Switches are ON in sampling phase which is approximately one half of a clock period.

Figure 41. Analog Input Stage

This differential input topology produces a high level

differential signal of 1.15 VPP for a total differential

of AC performance for high sampling rates. It also

input signal swing of 2.3 VPP. The maximum swing is

results in a high usable input bandwidth, especially

determined by the two reference voltages, the top

important for high intermediate-frequency (IF) or

reference (REFP, pin 29), and the bottom reference

undersampling applications. The ADS5500 requires

(REFM, pin 30).

each of the analog inputs (INP, INM) to be externally

The ADS5500 obtains optimum performance when

biased around the common-mode level of the

the analog inputs are driven differentially. The circuit

internal circuitry (CM, pin 17). For a full-scale

shown in Figure 42 shows one possible configuration

differential input, each of the differential lines of the

using an RF transformer.

input signal (pins 19 and 20) swings symmetrically

between CM + 0.575 V and CM – 0.575 V. This

means that each input is driven with a signal of up to

CM 0.575 V, so that each input has a maximum

Submit Documentation Feedback

ADS5500IPAPR Datenblatt(PDF) 22 Page - Texas Instruments

ADS5500IPAPR Datenblatt(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datenblatt Download

Link URL