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REVISION HISTORY

ADS5500

SBAS303F – DECEMBER 2003 – REVISED FEBRUARY 2007

REVISION

DATE

DESCRIPTION

0.0

12/03

Preliminary data sheet released

1.0

03/04

Data sheet updated to reflect RTM silicon

2.0

09/05

Added information regarding thermal pad size and thermal characteristics of the package.

Removed input current from Absolute Maximum Ratings table. Updated specifications to AGND and

DRGND. Added notes regarding the input voltage overstress requirements.

Changed minimum recommended sampling rate to 2 Msps.

Clarified the Electrical Characteristics measurement conditions.

Changed analog input common-mode current specification.

Removed maximum sampling rate from specification table.

Added Voltage Overload Recovery Time specification.

Changed offset temperature coefficient to units of mV/

°C.

Changed power dissipation reporting to separate analog and digital power dissipation.

Changed two-tone intermodulation distortion units to dBFS and updated the specification values to reflect

this change.

Clarified the Digital Characteristics measurement conditions.

Added min VOH and max VOL specifications.

Added data valid with respect to the input clock, output clock jitter, wakeup time, and output clock rise and

fall time parameters.

Clarified the Timing Characteristics measurement conditions.

Updated the timing diagram in Figure 1 to include tSTART and tEND timing parameters.

Added minimum and maximum specifications for various timing parameters.

Added section on Reset Timing.

Clarified serial interface data word format.

Clarified output capture test modes.

Simplified the information given in Table 3.

Updated the definitions section.

Clarified measurement conditions for the specifications plots.

Corrected text annotations on the WCDMA signal plot.

Added axis label to HD3 with DLL ON contour plot.

Updated Figure 4 to correct parameter values and improve readability.

Added 25-

Ω series resistors to ADC inputs in Figure 5.

Corrected text in Input Configuration section to accurately reflect the CM voltage decoupling depicted in

Figure 5.

Updated Equation 5 to match the new definition of common-mode input current and minimum sample rate.

Added 25-

Ω series resistors to ADC inputs in Figure 6.

Changed Power Supply Sequence section to reduce constraints on the power-up sequence.

Updated the Power Down section to reflect the newly specified 2 Msps minimum sampling rate.

Updated Output Information text to include information on the output data in over-range conditions, describe

data capture using the input clock, and add tables to specify timing parameters at various sampling rates.

3.0

10/05

Improved SNR performance parameters.

Updated Reference Circuit section to reflect that the 1-

Ω series resistors to REFP and REFM are now

optional.

Updated timing parameters in Table 5 through Table 8 to reflect revised silicon timing.

REV G

02/07

Added min/max specs for offset and gain errors

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