ST7SCR_07 datasheet(31/101 Pages) STMICROELECTRONICS

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ST7SCR

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POWER SAVING MODES (Cont’d)

8.3 HALT MODE

The HALT mode is the MCU lowest power con-

sumption mode. The HALT mode is entered by ex-

ecuting the HALT instruction. The internal oscilla-

tor is then turned off, causing all internal process-

ing to be stopped, including the operation of the

on-chip peripherals.

Note: The PLL must be disabled before a HALT

instruction.

When entering HALT mode, the I bit in the Condi-

tion Code Register is cleared. Thus, any of the ex-

ternal interrupts (ITi or USB end suspend mode),

are allowed and if an interrupt occurs, the CPU

clock becomes active.

The MCU can exit HALT mode on reception of ei-

ther an external interrupt on ITi, an end suspend

mode interrupt coming from USB peripheral, or a

reset. The oscillator is then turned on and a stabi-

lization time is provided before releasing CPU op-

eration. The stabilization time is 512 CPU clock cy-

cles.

After the start up delay, the CPU continues opera-

tion by servicing the interrupt which wakes it up or

by fetching the reset vector if a reset wakes it up.

Figure 22. HALT Mode Flow Chart

EXTERNAL

INTERRUPT*

RESET

HALT INSTRUCTION

512 CPU CLOCK

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CYCLES DELAY

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I-BIT

SET

CPU CLOCK

OSCILLATOR

PERIPH. CLOCK

I-BIT

OFF

CLEARED

OFF

Note: Before servicing an interrupt, the CC

during the interrupt routine and cleared when

the CC register is popped.

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