| Datenblatt-Suchmaschine für elektronische Bauteile |
|
ST7SCR Datenblatt(PDF) 39 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST7SCR Datenblatt(HTML) 39 Page - STMicroelectronics |
|
39 / 101 page ![]() ST7SCR 39/101 MISCELLANEOUS REGISTER 3 (MISCR3) Reset Value: 0000 0000 (00h) Read/Write This register is used to configure the edge and the level sensitivity of the Port A and Port C external interrupt. This means that all bits of a port must have the same sensitivity. If a write access modifies bits 7:4, it clears the pending interrupts. CTRL0_C, CTRL1_C : Sensitivity on port C CTRL0_A, CTRL1_A : Sensitivity on port A MISCELLANEOUS REGISTER 4 (MISCR4) Reser Value : 0000 0000 (00h). Read/Write Bit 7 = Reserved. Bit 6 = PLL_ON PLL Activation 0: PLL disabled 1: PLL enabled Note: The PLL must be disabled before a HALT instruction. Bit 5 = CLK_SEL Clock Selection This bit is set and cleared by software. 0: CPU frequency = 4MHz 1: CPU frequency = 8MHz Bits 4:1 = Reserved. Bit 0 = LOCK PLL status bit 0: PLL not locked. fCPU = fOSC external clock fre- quency. 1: PLL locked. fCPU = 4 or 8 MHz depending on CLKSEL bit. 70 CTR L1_A CTR L0_A CTR L1_C CTR L0_C --- - CTR L1_X CTR L0_X External Interrupt Sensitivity 0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge 70 - PLL _ON CLK_ SEL -- - - LOCK |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |