CMV2000 datasheet(27/87 Pages) AMSOSRAM

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CMV2000

Functional description

Datasheet

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DS000734

• v8-00 • 2025-Jul-07

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7.2.4

Input clock

The high-speed LVDS input clock (LVDS_CLK_N/P) defines the output data rate of the

CMV2000. The master clock (CLK_IN) must be 10 or 12 times slower depending on the

programmed bit mode setting. The maximum data rate of the output is 480 Mbps which results

in a LVDS_CLK_N/P of 480 MHz and a CLK_IN of 48 MHz in 10-bit mode and 40 MHz in 12-

bit mode. The minimum frequencies are 5 MHz for CLK_IN and 50MHz for LVDS_CLK_N/P.

Any frequency between the minimum and maximum can be applied by the user and will result

in a corresponding output data rate, like showed in Table 6.

Table 6: Output data rate depending on the CLK_IN and bit mode

CLK_IN

LVDS_CLK 10-bit

LVDS_CLK 12-bit

5 MHz

50 MHz

60 MHz

40 MHz

400 MHz

480 MHz

48 MHz

480 MHz

N/A

The rising edge LVDS input clock can have a limited delay with respect to the rising edge of

the master input clock, depending on clock speed. In Figure 15, the skew limits are shown for

different clock speeds and for an LVDS clock that rises before and after the master input clock.

To assure proper working of the sensor, the skew of the LVDS clock should always fall within

these limits, shown as the green area.

CMV2000 Datenblatt(PDF) 27 Page - ams-OSRAM AG