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CMV2000 Datenblatt(PDF) 10 Page - ams-OSRAM AG |
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CMV2000 Datenblatt(HTML) 10 Page - ams-OSRAM AG |
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10 / 87 page ![]() CMV2000 Pinout Datasheet • PUBLIC • Document Feedback DS000734 • v8-00 • 2025-Jul-07 10 / 87 / 3.3 Pining list The pin list of the CMV2000 can be found below for the µPGA and LCC packages. The pin list for the LGA package is the same as for the µPGA package. Table 3: Pinout in detail µPGA LCC Pin name Description Type G7 60 Tana Test pin for analog signals (optional) Analog output D12 42 REF_ADC Reference for ADC testing (decouple with 100 nF to ground) Bias E10 41 SG_ADC Signal for ADC testing (decouple with 100 nF to ground) Bias E11 40 Vramp1 Start voltage first ramp (decouple with 100 nF to ground) Bias E12 39 Vramp2 Start voltage second ramp (decouple with 100 nF to ground) Bias F6 62 Vpch_H Precharge high voltage (decouple with 100 nF to ground) Bias H8 57 Vres_L Reset low voltage (decouple with 100 nF to ground) Bias F8 54 Vtf_l2 Transfer low voltage 2 (decouple with 100 nF to ground) Bias H9 53 Vtf_l3 Transfer low voltage 3 (decouple with 100 nF to ground) Bias D11 43 VREF Reference for column amps (decouple with 100 nF to ground) Bias F9 51 Col_load Decouple with 100 nF to ground Bias G9 52 Col_amp Decouple with 100 nF to ground Bias G6 63 CMD_N Decouple with 100 nF to ground Bias G11 45 Vbgap Decouple with 100 nF to ground Bias H10 50 COL_PC Decouple with 100 nF to ground Bias H11 44 LVDS Decouple with 100 nF to ground Bias G5 66 CMD_P Decouple with 100 nF to VDD33 Bias F5 65 CMD_P_INV Decouple with 100 nF to VDD33 Bias F10 48 ramp Decouple with 100 nF to VDD33 Bias G10 49 ADC Decouple with 100 nF to VDD33 Bias G8 55 Vtf_l1 Transfer low voltage 1 (connect to ground) Bias H5 67 SYS_RES_N Input pin for sequencer reset Digital input E1 80 CLK_IN Master input clock Digital input F2 76 FRAME_REQ Frame request pin Digital input G3 72 T_EXP2 Input pin for external exposure mode (optional) Digital input |
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