910GL datasheet(79/426 Pages) INTEL

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Host Bridge/DRAM Controller Registers (D0:F0)

Datasheet

4.1.17

DEVEN—Device Enable (D0:F0)

PCI Device:

Address Offset:

54h

Default Value:

00000019h

Access:

R/W

Size:

32 bits

This register allows for enabling/disabling of PCI devices and functions that are within the

(G)MCH.

Bit

Access &

Default

Description

R/W

82915G/82915P/82915PL (G)MCH:

PCIEXBAR Enable (PCIEXBAREN):

0 = The PCIEXBAR register is disabled. Memory read and write transactions

proceed as if there were no PCIEXBAR register. PCIEXBAR bits 31:28 are

R/W with no functionality behind them.

1 = The PCIEXBAR register is enabled. Memory read and write transactions

whose address bits 31:28 match PCIEXBAR 31:28 will be translated to

configuration reads and writes within the (G)MCH. These translated cycles

are routed as shown in the table above.

82915GV/82915GL/82910GL GMCH:

Reserved.

Reserved

R/W

DMIBAR Enable (DMIBAREN):

0 = DMIBAR is disabled and does not claim any memory.

1 = DMIBAR memory mapped accesses are claimed and decoded appropriately.

R/W

MCHBAR Enable (MCHBAREN):

0 = MCHBAR is disabled and does not claim any memory.

1 = MCHBAR memory mapped accesses are claimed and decoded

appropriately.

R/W

EPBAR Enable (EPBAREN):

0 = EPBAR is disabled and does not claim any memory.

1 = EPBAR memory mapped accesses are claimed and decoded appropriately.

26:5

Reserved

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