910GL datasheet(61/426 Pages) INTEL

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Datasheet

To access this space (steps 1, 2, 3 are performed only once by BIOS)

Use the PCI compatible configuration mechanism to enable the PCI Express enhanced

configuration mechanism by writing 1 to bit 31 of the DEVEN register.

Use the PCI compatible configuration mechanism to write an appropriate PCI Express base

address into the PCIEXBAR register.

Calculate the host address of the register you wish to set using (PCI Express base + (bus

number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) + (1 B * offset

within the function) = host address).

Use a memory write or memory read cycle to the calculated host address to write to or read

from that register.

Base

20 19

15 14

Config_Write

Bus

Device

Function Extended

Number

PCI Express Configuration Writes

Internally the host interface unit translates writes to PCI Express extended configuration space to

configurations on the backbone. Writes to extended space are posted on the FSB, but non-posted

on the PCI Express* x16 Graphics Interface or DMI pins (i.e., translated to configuration writes).

See the PCI Express Specification for more information on both the PCI 2.3 compatible and PCI

Express enhanced configuration mechanism and transaction rules.

910GL Datenblatt(PDF) 61 Page - Intel Corporation