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Datasheet

Item

Description

R/WSC

Read / Write Self Clear bit(s). These bits can be read and written. When the bit is ‘1’,

hardware may clear the bit to ‘0’ based upon internal events, possibly sooner than any

subsequent read could retrieve a ‘1’.

R/WSC/L

Read / Write Self Clear / Lockable bit(s). These bits can be read and written. When the

bit is ‘1’, hardware may clear the bit to ‘0’ based upon internal events, possibly sooner

than any subsequent read could retrieve a ‘1’. Additionally there is a bit (which may or

may not be a bit marked R/W/L) that, when set, prohibits this bit field from being

writeable (bit field becomes Read Only).

R/WC

Read Write Clear bit(s). These bits can be read and written. However, a write of ‘1’

clears (sets to ‘0’) the corresponding bit(s) and a write of ‘0’ has no effect.

R/WO

Write Once bit(s). Once written, bits with this attribute become Read Only. These bits

can only be cleared by a Reset.

Write Only. Whose bits may be written, but will always-return zeros when read. They are

used for write side effects. Any data written to these registers cannot be retrieved.

Reserved Bits

Some of the (G)MCH registers described in this section contain reserved bits. These

bits are labeled "Reserved”. Software must deal correctly with fields that are reserved.

On reads, software must use appropriate masks to extract the defined bits and not rely

on reserved bits being any particular value. On writes, software must ensure that the

values of reserved bit positions are preserved. That is, the values of reserved bit

positions must first be read, merged with the new values for other bit positions and then

written back. Note the software does not need to perform read, merge, and write

operation for the configuration address register.

Reserved

Registers

In addition to reserved bits within a register, the (G)MCH contains address locations in

the configuration space of the Host Bridge entity that are marked either "Reserved" or

“Intel Reserved”. The (G)MCH responds to accesses to “Reserved” address locations

by completing the host cycle. When a “Reserved” register location is read, a zero value

is returned. (“Reserved” registers can be 8-, 16-, or 32-bits in size). Writes to

“Reserved” registers have no effect on the (G)MCH. Registers that are marked as “Intel

Reserved” must not be modified by system software. Writes to “Intel Reserved”

registers may cause system failure. Reads from “Intel Reserved” registers may return a

non-zero value.

Default Value

Upon a Full Reset, the (G)MCH sets its entire set of internal configuration registers to

predetermined default states. Some register values at reset are determined by external

strapping options. The default state represents the minimum functionality feature set

required to successfully bringing up the system. Hence, it does not represent the

optimal system configuration. It is the responsibility of the system initialization software

(usually BIOS) to properly determine the DRAM configurations, operating parameters

and optional system features that are applicable, and to program the (G)MCH registers

accordingly.

910GL Datenblatt(PDF) 54 Page - Intel Corporation

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