910GL datasheet(168/426 Pages) INTEL

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Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

168

Datasheet

8.1.54

VC1RSTS—VC1 Resource Status (D1:F0)

PCI Device:

Address Offset:

126h

Default Value:

0000h

Access:

Size:

16 bits

This register reports the Virtual Channel specific status.

Bit

Access &

Default

Description

15:2

Reserved

VC1 Negotiation Pending

0 = The VC negotiation is complete.

1 = The VC resource is still in the process of negotiation (initialization or

disabling).

This bit indicates the status of the process of Flow Control initialization. It is set by

default on Reset, as well as when the corresponding Virtual Channel is Disabled

or the Link is in the DL_Down state. It is cleared when the link successfully exits

the FC_INIT2 state

Before using a Virtual Channel, software must check whether the VC Negotiation

Pending fields for that Virtual Channel are cleared in both Components on a Link.

Reserved

8.1.55

RCLDECH—Root Complex Link Declaration Enhanced

Capability Header (D1:F0)

PCI Device:

Address Offset:

140h

Default Value:

00010005h

Access:

Size:

32 bits

This capability declares links from this element (PCI Express* x16 Graphics Interface) to other

elements of the root complex component to which it belongs. See the PCI Express specification

for link/topology declaration requirements.

Bit

Access &

Default

Description

31:20

000h

Pointer to Next Capability: This is the last capability in the PCI Express*

extended capabilities list.

19:16

Link Declaration Capability Version: Hardwired to 1 to indicate compliances

with the 1.0a version of the PCI Express specification.

15:0

0005h

Extended Capability ID: Value of 0005h identifies this linked list item (capability

structure) as being for PCI Express Link Declaration Capability.

Note:

See corresponding Egress Port Link Declaration Capability registers for diagram of Link

Declaration Topology.

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