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RL78 Datenblatt(PDF) 63 Page - Renesas Technology Corp

Teilenummer RL78
Bauteilbeschribung  True Low Power Platform (as low as 66 ?쵡/MHz, and 0.60 ?쵡 for RTC LVD), 1.6 V to 5.5 V operation
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RL78 Datenblatt(HTML) 63 Page - Renesas Technology Corp

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RL78/G14
2. ELECTRICAL SPECIFICATIONS
R01DS0053EJ0100 Rev. 1.00
Page 63 of 97
Feb 21, 2012
Caution
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.5
Peripheral Functions Characteristics
2.5.1
Serial array unit
UART mode connection diagram (during communication at same potential)
UART mode bit width (during communication at same potential) (reference)
Note 1.
Transfer rate in the SNOOZE mode is MAX. 9600 bps and MIN. 4800 bps.
Note 2.
The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V
 EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V
 EVDD0 < 2.4 V : MAX. 1.3 Mbps
1.6 V
 EVDD0 < 1.8 V : MAX. 0.6 Mbps
Caution
Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
(1)
During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = -40 to +85
C, 1.6 V EVDD0 = EVDD1 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transfer rate Note 1
fMCK/6 Note 2
bps
Theoretical value of the maximum transfer
rate fCLK = 32 MHz, fMCK = fCLK
5.3
Mbps
TxDq
RxDq
User’s device
Rx
Tx
RL78/G14
Baud rate error tolerance
TxDq
RxDq
High-/Low-bit width
1/Transfer rate



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