RL78 datasheet(64/100 Pages) RENESAS

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RL78/G14

2. ELECTRICAL SPECIFICATIONS

R01DS0053EJ0100 Rev. 1.00

Page 64 of 97

Feb 21, 2012

Caution

The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.

Note 1.

The value must also be 2/fCLK or more.

Note 2.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp

↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 3.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp

↓” when

DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 4.

When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from

SCKp

↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

Note 5.

Using the fMCK within 24 MHz.

Note 6.

C is the load capacitance of the SCKp and SOp output lines.

Caution

Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using

port input mode register g (PIMg) and port output mode register g (POMg).

Remark 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.

Remark 2.

p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),

g: PIM and POM numbers (g = 1)

Remark 3.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00))

(2)

During communication at same potential (CSI mode) (master mode (fMCK/2), SCKp... internal clock output)

(TA = -40 to +85

C, 2.7 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCKp cycle time

tKCY1

2.7 V

 EVDD0  5.5 V

62.5 Note 1

SCKp high-/low-level width

tKH1,

tKL1

4.0 V

 EVDD0  5.5 V

tKCY1/2 - 7

2.7 V

 EVDD0  5.5 V

tKCY1/2 - 10

SIp setup time (to SCKp

↑) Note 2

tSIK1

4.0 V

 EVDD0  5.5 V

2.7 V

 EVDD0  5.5 V

33 Note 5

SIp hold time (from SCKp

↑) Note 3

tKSI1

2.7 V

 EVDD0  5.5 V

Delay time from SCKp

↓ to SOp output

Note 4

tKSO1

C = 20 pF Note 6

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