RL78 datasheet(89/100 Pages) RENESAS

89 / 100 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS

R01DS0053EJ0100 Rev. 1.00

Page 89 of 97

Feb 21, 2012

Caution

The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.

Note 1.

Excludes quantization error (±1/2 LSB).

Note 2.

This value is indicated as a ratio (% FSR) to the full-scale value.

(2)

When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1),

target ANI pin: ANI16 to ANI20 (supply ANI pin to EVDD0)

(TA = -40 to +85

C, 1.6 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) =

AVREFP, Reference voltage (-) = AVREFM = 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

RES

810

bit

Overall error Notes 1, 2

AINL

10-bit resolution

AVREFP = VDD

1.8 V

 VDD  5.5 V

1.2

5.0

LSB

1.6 V

 VDD  5.5 V

1.2

8.5

LSB

Conversion time

tCONV

10-bit resolution

AVREFP = VDD

3.6 V

 VDD  5.5 V

2.125

s

2.7 V

 VDD  5.5 V

3.1875

s

1.8 V

 VDD  5.5 V

s

1.6 V

 VDD  5.5 V

s

Zero-scale error Notes 1, 2

EZS

10-bit resolution

AVREFP = VDD

1.8 V

 VDD  5.5 V

0.35

% FSR

1.6 V

 VDD  5.5 V

0.60

% FSR

Full-scale error Notes 1, 2

EFS

10-bit resolution

AVREFP = VDD

1.8 V

 VDD  5.5 V

0.35

% FSR

1.6 V

 VDD  5.5 V

0.60

% FSR

Integral linearity error Note 1

ILE

10-bit resolution

AVREFP = VDD

1.8 V

 VDD  5.5 V

3.5

LSB

1.6 V

 VDD  5.5 V

6.0

LSB

Differential linearity error

Note 1

DLE

10-bit resolution

AVREFP = VDD

1.8 V

 VDD  5.5 V

2.0

LSB

1.6 V

 VDD  5.5 V

2.5

LSB

Reference voltage (+)

AVREFP

1.6

VDD

Analog input voltage

VAIN

AVREFP

and

EVDD0

VBGR

2.4 V

 VDD  5.5 V,

HS (high-speed main) mode

1.38

1.45

1.5

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