RL78 datasheet(85/100 Pages) RENESAS

85 / 100 page

RL78/G14

2. ELECTRICAL SPECIFICATIONS

R01DS0053EJ0100 Rev. 1.00

Page 85 of 97

Feb 21, 2012

Caution

The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.

Note 1.

Use it with EVDD0

 Vb.

Note 2.

Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.

Caution

Select the TTL input buffer and the N-ch open drain output (EVDD0 tolerance) mode for the SDAr pin and the N-ch

open drain output (EVDD0 tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port

output mode register g (POMg).

(Remarks are listed on the next page.)

(10) Communication at different potential (2.5 V, 3 V) (simplified I2C mode)

(TA = -40 to +85

C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

(2/2)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Data setup time (reception)

tSU:DAT

4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 50 pF, Rb = 2.7 k



1/fMCK + 135

Note 2

2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb < 2.7 V,

Cb = 50 pF, Rb = 2.7 k



1/fMCK + 135

Note 2

4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 100 pF, Rb = 2.8 k



1/fMCK + 190

Note 2

2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb < 2.7 V,

Cb = 100 pF, Rb = 2.7 k



1/fMCK + 190

Note 2

1.8 V

 EVDD0 < 3.3 V,

1.6 V

 Vb  2.0 V Note 1,

Cb = 100 pF, Rb = 5.5 k



1/fMCK + 190

Note 2

Data hold time (transmission)

tHD:DAT

4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 50 pF, Rb = 2.7 k



305

2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb < 2.7 V,

Cb = 50 pF, Rb = 2.7 k



305

4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 100 pF, Rb = 2.8 k



355

2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb < 2.7 V,

Cb = 100 pF, Rb = 2.7 k



355

1.8 V

 EVDD0 < 3.3 V,

1.6 V

 Vb  2.0 V Note 1,

Cb = 100 pF, Rb = 5.5 k



405

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