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RL78 Datenblatt(PDF) 87 Page - Renesas Technology Corp

Teilenummer RL78
Bauteilbeschribung  True Low Power Platform (as low as 66 ?쵡/MHz, and 0.60 ?쵡 for RTC LVD), 1.6 V to 5.5 V operation
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RL78 Datenblatt(HTML) 87 Page - Renesas Technology Corp

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RL78/G14
2. ELECTRICAL SPECIFICATIONS
R01DS0053EJ0100 Rev. 1.00
Page 87 of 97
Feb 21, 2012
Caution
The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
2.5.2
Serial interface IICA
Note 1.
The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
Fast mode: Cb = 320 pF, Rb = 1.1 k
Fast mode plus: Cb = 120 pF, Rb = 1.1 k
IICA serial transfer timing
(TA = -40 to +85
C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
Standard
Mode
Fast Mode
Fast Mode
Plus
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock frequency
fSCL
Fast mode plus:
fCLK
 10 MHz
2.7 V
 EVDD0  5.5 V
0
1000
kHz
Fast mode:
fCLK
 3.5 MHz
1.8 V
 EVDD0  5.5 V
0
400
kHz
Normal mode:
fCLK
 1 MHz
1.6 V
 EVDD0  5.5 V
0
100
kHz
Setup time of restart
condition Note 1
tSU:STA
4.7
0.6
0.26
s
Hold time
tHD:STA
4.0
0.6
0.26
s
Hold time when SCLA0 = “L”
tLOW
4.7
1.3
0.5
s
Hold time when SCLA0 = “H”
tHIGH
4.0
0.6
0.26
s
Data setup time (reception)
tSU:DAT
250
100
50
ns
Data hold time (transmission)
Note 2
tHD:DAT
03.450
0.9
0
s
Setup time of stop condition
tSU:STO
4.0
0.6
0.26
s
Bus-free time
tBUF
4.7
1.3
0.5
s
tSU: DAT
tHD: STA
Restart
condition
SCL0
SDA0
tLOW
tHIGH
tSU: STA
tHD: STA
tSU: STO
Stop
condition
Stop
condition
Start
condition
tHD: DAT
tLOW



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