AM7968-125JC datasheet(20/127 Pages) AMD

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AMD

Am7968/Am7969

Am7968 Transmitter Functional Block

Description

(Refer to page 1)

Crystal Oscillator/Clock Generator

The serial link speed is derived from a master frequency

source (byte rate). This source can either be the built-in

Crystal Oscillator, or a clock signal applied through the

1 pin. This signal is buffered and sent to the CLK out-

put when Am7968 Transmitter is in Local mode.

CLK (input is multiplied by ten (8-bit mode), eleven (9-bit

mode), or twelve (10-bit mode), using the internal PLL to

create the bit rate.

The working frequency can be varied between 3.3 MHz

and 17.5 MHz. The crystal frequency required to

achieve the maximum 175 Mbaud on the serial link, and

the resultant usable data transfer rate will be:

Crystal

Am7968-125 Input and Am7969-125

Internal

Mode

Frequency

Maximum Parallel Throughput

Divide Ratio

8-Bit

12.50 MHz

80 ns/pattern (100 Mbit/sec)

125/10

9-Bit

11.36 MHz

88 ns/pattern (102 Mbit/sec)

125/11

10-Bit

10.42 MHz

96 ns/pattern (104 Mbit/sec)

125/12

Crystal

Am7968-175 Input and Am7969-175

Internal

Mode

Frequency

Maximum Parallel Throughput

Divide Ratio

8-Bit

17.50 MHz

57.1 ns/pattern (140 Mbit/sec)

175/10

9-Bit

15.90 MHz

62.8 ns/pattern (143 Mbit/sec)

175/11

10-Bit

14.58 MHz

68.5 ns/pattern (145 Mbit/sec)

175/12

Input Latch

The Am7968’s Input Latch accommodates asynchro-

nous strobing of Data and Command by being divided

into two stages.

STRB is asserted when both stages are empty, Data

or Command bits are transferred directly to the second

stage of the Input Latch and

ACK rises shortly after

STRB. This pattern is now ready to move to the Encoder

Latch at the next falling edge of

CLK.

An input pattern is strobed into the first stage of the Input

Latch only when the second stage is BUSY (contains

previously stored data). The Transmitter will be BUSY

when

STRB is asserted a second time in a given CLK

cycle. Contents of the first stage are not protected from

subsequent

STRBs within the same CLK cycle. At the

falling edge of

CLK, previously stored data is transferred

from the second stage to the Encoder Latch and the new

data is clocked into the second stage of the Input Latch.

If in Local mode,

ACK will rise at this time.

Encoder Latch

Input to the Encoder Latch is clocked by an internal sig-

nal which is synchronous with the shifted byte being

sent on the serial link. Whenever a new input pattern is

strobed into the Input Latch, the data is transferred to the

Encoder Latch at the next opportunity.

Data Encoder

Encodes twelve data inputs (8, 9, 10 Data bits or 4, 3, 2

Command inputs) into 10, 11, or 12 bits. The Command

data inputs control the transmitted symbol. If all Com-

mand inputs are LOW, the symbol for the Data bits will

be sent. If Command inputs have any other pattern then

the symbol representing that Command will be

transmitted.

Shifter

The Shifter is parallel-loaded from the Encoder at the

first available byte boundary, and then shifted until the

next byte boundary. The Shifter is being serially loaded

at all times. As data is being shifted out of the Transmit-

ter, the shifter fills from the LSB. If parallel data is avail-

able at the end of the byte, it is parallel-loaded into the

Shifter and begins shifting out during the next clock cy-

cle. Otherwise, the serially loaded data fills the next

byte. The serial data which loads into the Shifter is gen-

erated by an internal state machine which generates a

repeating Sync pattern.

Media Interface

The Media Interface is differential ECL, referenced to

+5 V. It is capable of driving lines terminated with 50

Ω to

(VCC - 2.0) volts.

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