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AM7968-125JC Datenblatt(PDF) 76 Page - Advanced Micro Devices |
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AM7968-125JC Datenblatt(HTML) 76 Page - Advanced Micro Devices |
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76 / 127 page ![]() AMD 72 TAXIchip Integrated Circuits Technical Manual Figure 6-1 Transmitter and Receiver Decoupling Layouts VCC1 (TTL) VCC2 (ECL) GND1 VCC3 (CML) GND2 (CML) Am7968 AB C2 C1 C3 6 5 22 C1 C3 7 21 C1 C3 Leads must be very short (less than 1/4 ″) C1 = 0.1 µF (ceramic) C2 = 1 µF Tantalum C3 = 0.01 µF (ceramic) VCC Plane GND1 VCC2 (CML) GND2 Am7969 D C2 7 20 8 21 C1 C3 Transmitter Receiver C3 To further decouple the TAXIchip set, it is highly recommended that ferrite beads be inserted at locations A, B and D. 12330E-19 C1 VCC Plane VCC1 (TTL) Figure 6-3 Jogs and Glitches in the Clock Line Normal Overshoot < 0.5 V CLK or X1 Jog or Glitch Normal Undershoot < 0.5 V 12330E-20 3. Keep all bypass capacitors as close to the power pins of the device as possible. Lead lengths should be minimized. 4. Use high quality RF grade capacitors such as type COG or X7R. Use of Z5U capaci- tors is not recommended. 5. Ensure that the power supply does not have more that 100 mV of peak-to-peak noise at any of the TAXI Vcc pins. Make this check while the TAXls are sending random data. 6. While CLK can drive four X1 inputs or several TTL loads, the highest performance can be achieved by reducing the load on the CLK pin. Care should be taken to en- sure that no jogs or glitches occur in the CLK signal as shown in Figure 6-3. If pre- sent, these glitches will be passed onto the PLL and cause an occasional error. Serial Lines 7. Run serial outputs parallel to each other, or one on top of the other at all times and route them away from the Transmitter. Do the same for serial inputs on the Receiver. Running these serial traces adjacently will minimize noise caused by these extremely fast signals on other traces. Use of strip lines for serial signals is recommended. |
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