AM7968-125JC datasheet(14/127 Pages) AMD

14 / 127 page

AMD

Am7968/Am7969

FUNCTIONAL DESCRIPTION

System Configuration

The TAXIchip system provides a means of connecting

parallel data systems over a serial link (Figure 2). In

LOCAL Mode (normal operation mode) each TX/RX

pair is connected over a serial link which can be a Fiber

Optic or Copper Media (Figure 3).

The Am7968 Transmitter accepts inputs from a sending

host system using a simple

STRB/ACK handshake.

Parallel bits are saved by the Am7968’s input latch on

the rising edge of a

STRB input. The input latch can be

updated on every

CLK cycle; if it still contains previously

stored data when a second

STRB pulse arrives, Data is

stored in the input latch, and the second

ACK response

is delayed until the next

CLK cycle.

The inputs to an Am7968 Transmitter can be either Data

or Command and may originate from two different parts

of the host system. A byte cycle may contain Data or

Command, but not both. Data represents the normal

data channel message traffic between host systems.

Commands can come from a communication control

section of the host system. Commands occur at a rela-

tively infrequent rate but have priority over Data. Exam-

ples include communication specific commands such

as REQUEST-TO-SEND or CLEAR-TO-SEND; or

application specific commands such as MESSAGE-

ADDRESS-FOLLOWS, MESSAGE-TYPE-FOLLOWS,

INITIALIZE YOUR SYSTEM, ERROR, RETRANSMIT,

HALT, etc.

The Am7968 Transmitter switches between Data and

Command by examining Command input patterns. All

0s on Command input pins cause information on the

Am7968’s Data input pins to be latched into the device

on the rising edge of

STRB. All other Command patterns

cause a Command symbol to be sent in response to an

input strobe. The pattern on the Data inputs is ignored

when a Command symbol is sent. In either case, if there

is no

STRB before the next byte boundary, a Sync sym-

bol will be transmitted. The sync pattern maintains link

synchronization and provides an adequate signal transi-

tion density to keep the Receiver Phase-Locked-Loop

(PLL) circuits in lock. It was chosen for its unique pattern

which never occurs in any Data or Command mes-

sages. This feature allows Sync to be used to establish

byte boundaries.

The Sync pattern utilized by TAXIchip set keeps the

automatic gain control (AGC) fiber-optic transceiver cir-

cuits in their normal range because the pattern has zero

DC offset.

The Am7969 Receiver detects the difference between

Data and Command patterns and routes each to the

proper Output Latch. When a new Data pattern enters

the output latch,

DSTRB is pulsed and Command

information remains unchanged. If a Command pattern

is sent to the output latch or if Sync is received,

CSTRB

is pulsed and Data outputs remain in their previous

state. Reception of a Sync pattern clears the Command

outputs to all 0’s, since Sync is a legal command.

Noise-induced bit errors can distort transmitted bit pat-

terns. The Am7969 Receiver logic detects most noise-

induced transmission errors. Invalid bit patterns are

recognized and indicated by the assertion of the viola-

tion (

VLTN) output pin. This signal rises to a logic “1”

state at the same time that Data or Command outputs

change and remains HIGH until a valid pattern is

detected by the Data Decoder. The error detection

method used in the Receiver cannot identify bit

errors which transform one valid Command or Data pat-

tern to another. Fault-sensitive systems should use ad-

ditional error checking mechanisms to guarantee

message integrity.

Am7968 Transmitter

The Transmitter accepts messages from its parallel in-

put pins (Command or Data). Once latched into an

Am7968, a parallel message is encoded, serialized, and

shifted out to the serial link. The idle time between trans-

mitted bytes (evident by lack of STRB) is filled with

Sync bytes.

Am7969 Receiver

Receivers accept differential signals on the

SERIN+/

SERIN– input pins. This information, previously

encoded by an Am7968 Transmitter, is loaded into

a decoder.

When serial patterns are received, they are decoded

and routed to the appropriate outputs. If the received

message is a Command, it is stored in the output latch,

appears at the Command output pins, and

CSTRB is

pulsed; Data output pins continue holding the last Data

byte and

DSTRB stays inactive. If a Data message fol-

lows the reception of a Command, Command output

pins continue holding the previous Command byte and

CSTRB stays inactive. The command outputs will retain

their states until another Command signal is received

(Sync is considered to be a valid command which, when

decoded, sets Command outputs to “0” and issues a re-

sulting

CSTRB).

Byte Width

The TAXIchip set has twelve parallel interface pins

which are designated to carry either Command or Data

bits. The Data Mode Select (

DMS) pin on each chip can

be set to select one of three modes of operation: eight

Data and four Command bits, nine Data and three Com-

mand, or ten Data and two Command. This allows the

system designer to select the byte-width which best

suits system needs.

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