AM7968-125JC datasheet(100/127 Pages) AMD

100 / 127 page

AMD

TAXIchip Integrated Circuits Technical Manual

TAXI Technical Information Publication #89-02

Subject: TAXlchip RESET Pin Function

Question:

How long must the

RESET pin be held low in order to insure that the TAXIchip has

reset?

Answer:

The

RESET pin is level sensitive and after a LOW input level is asserted it instantane-

ously forces the Phase Lock Loop (PLL) to its lowest possible frequency (approximately

5 to 10 MHz). A 1 ms LOW pulse should allow sufficient time for the PLL to reach a

stable state. Preliminary tests conducted in the lab reported that for the full TAXI

frequency and temperature range, the time required to recover from a reset was less

than 100

µs.

Resetting is intended to allow graceful recovery from the rare occurrence of a PLL

lock-up due to noise bursts on the serial data lines, as may occur when light is removed

from certain optical links. In a fiber-optic coupled system, loss of optical signal may

cause the optical receiver to oscillate, causing the TAXI Receiver to track the oscillation

to an indeterminate frequency. Care must be taken to avoid the oscillation, or a reset

can be used to recover from it. After reset, the PLL begins tracking incoming data, and

the byte boundary remains undefined until the transmitted data includes a Sync (JK).

The Sync is a unique bit pattern which forces the TAXI Receiver to align itself to the

correct byte boundary.

In a coaxial system when a loss of incoming signal drive occurs, there will be no data for

the TAXI Receiver to track. This

quiet state will be interpreted as a continuous data

pattern. The Receiver decodes this

Quiet-Line-State differently depending upon the

operational mode selected: 8-bit, 9-bit, or 10-bit. In 8-bit mode the TAXI Receiver will

generate continuous CSTRBs with command outputs all high (

F Hex). In 9-bit or 10-bit

modes there is no defined interpretation of an incoming quiet data stream thus generat-

ing continuous CSTRBs and forcing the violation output (VLIN) to be continuously high.

Further information on the effects of incoming signal drive loss is available in TAXI TIP

#89-01,

Receiver Response to Loss of Input Signal.

AM7968-125JC Datenblatt(PDF) 100 Page - Advanced Micro Devices