AM7968-125JC datasheet(117/127 Pages) AMD

117 / 127 page

AMD

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TAXIchip Integrated Circuits Technical Manual

active High, without any additional logic. The VLTN signal is used for both Command

and Data violations. Buffering of the DSTRB and VLTN signals may be necessary as

illustrated in Figure 15 to meet the drive requirements of the first column of registers.

Data/Command Output Note:

In this system, when a nonSync Command byte is received the data line values

corresponding to that byte will change to the values last output from the

TAXI Receiver

data lines. Conversely, when a data byte is received the command line values for that

byte will change to the values last output from the

TAXI Receiver command lines. This is

a characteristic of the example given and depends on how the command and data

information is latched.

Altering the Number of Output Bytes:

The above described design is an example of a four byte cascaded serial data receiving

system. The same design techniques can be used to expand or reduce the number of

bytes output at a time by the system. The considerations that should be taken into

account for an altered system deal with board space and part cost in accordance with

the requirements of the situation at hand. For board space note see the PAL Usage

section below.

PAL Usage:

In this system, the use of a PAL could greatly reduce the amount of board space used.

The PAL could incorporate all of the flip-flops and buffering logic as well as the first

column of registers that capture the system information. The reason a PAL was not

used in the system described above was to help ensure the understanding of the design

concept. For this application it is recommended that the timing considerations men-

tioned before should be investigated to ensure proper operation of the system.

AM7968-125JC Datenblatt(PDF) 117 Page - Advanced Micro Devices