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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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PC87413 Datenblatt(PDF) 71 Page - National Semiconductor (TI) |
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PC87413 Datenblatt(HTML) 71 Page - National Semiconductor (TI) |
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71 / 257 page  3.0 Device Architecture and Configuration (Continued) Revision 1.2 71 www.national.com 3.14.2 Logical Device 7 (GPIO) Configuration Table 25 lists the configuration registers that affect the GPIO. Only the last three registers (F0h - F2h) are described here. See Section 3.2.3 on page 40 for a detailed description of the other configuration registers. The standard configuration reg- isters are powered by VDD, however the specific configuration registers are powered by VSB. Table 25. GPIO Configuration Register Figure 6 shows the organization of these registers: Figure 6. Organization of GPIO Pin Registers Index Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.2.3 on page 40). R/W VDD 00h 60h Base Address MSB register. R/W VDD 00h 61h Base Address LSB register. Bits 4-0 (for A4-0) are read-only 00000b. R/W VDD 00h 70h Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W VDD 03h 74h Report no DMA assignment. RO VDD 04h 75h Report no DMA assignment. RO VDD 04h F0h GPIO Pin Select register (GPSEL). R/W VSB 00h F1h GPIO Pin Configuration register 1 (GPCFG1). R/W VSB See text F2h GPIO Pin Event Routing register (GPEVR). R/W VSB 01h F3h GPIO Pin Configuration register 2 (GPCFG2). R/W VSB 00h Port 4, Pin 0 Port 5, Pin 0 Port 6, Pin 0 GPIO Pin Configuration Registers Pin Select Port Select Port 0, Pin 0 GPIO Pin Select Register GPIO Pin Event Routing Register Port 0, Pin 7 Port 0 Port 6 Pin 0 Pin 7 Port 1, Pin 0 Port 2, Pin 0 Port 3, Pin 0 Port 1 Pin 0 Pin 7 Port 4 Port 1, Pin 0 Port 4, Pin 0 Port 1, Pin 7 (Index F0h) (Index F1h) (Index F2h) (Index F3h) |
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