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PC87413 Datenblatt(PDF) 87 Page - National Semiconductor (TI) |
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PC87413 Datenblatt(HTML) 87 Page - National Semiconductor (TI) |
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87 / 257 page ![]() 3.0 Device Architecture and Configuration (Continued) Revision 1.2 87 www.national.com 3.16 REAL TIME CLOCK (RTC) CONFIGURATION 3.16.1 General Description The RTC provides timekeeping and calendar management capabilities. It uses a 32.768 KHz signal as the basic clock for timekeeping. The RTC also includes 242 bytes of battery-backed RAM for general-purpose use. The RTC runtime registers are shown in Section 8.3.2 on page 150. These registers are VPP powered. 3.16.2 Logical Device 10 (RTC) Configuration Table 30 lists the configuration registers that affect the Real Time Clock. The standard configuration registers (see Section 3.2.3 on page 40) are powered by VDD. The specific configuration registers are powered by VSB. Table 30. RTC Configuration Registers Index RTC Configuration Register or Action Type Power Well Reset 30h Activate (see Section 3.3.1 on page 43). When bit 0 is cleared, the runtime registers of this logical device are not accessible. R/W VDD 00h 60h Standard Base Address MSB register. R/W VDD 00h 61h Standard Base Address LSB register. Bit 0 (for A0) is read only 0b. R/W VDD 70h 62h Extended RAM Base Address MSB register. R/W VDD 00h 63h Extended RAM Base Address LSB register. Bit 0 (for A0) is read only 0b. R/W VDD 72h 70h RTC Interrupt Number and Wake-Up on IRQ Enable register. R/W VDD 08h 71h RTC Interrupt Type. Bit 1 is read/write; other bits are read only. R/W VDD 00h 74h Report no DMA assignment. RO VDD 04h 75h Report no DMA assignment. RO VDD 04h F0h RAM Lock Register (RLR). R/W1S VSB 00h F1h Date-of-Month Alarm Register Offset (DOMAO). R/W VSB 00h F2h Month Alarm Register Offset (MONAO). R/W VSB 00h F3h Century Register Offset (CENO). R/W VSB 00h |
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